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PDF AT91M40400 Data sheet ( Hoja de datos )
| Número de pieza | AT91M40400 | |
| Descripción | 16/32-Bit Microcontroller | |
| Fabricantes | ATMEL Corporation | |
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Features
• Incorporates the ARM7TDMI ™ ARM Thumb processor
– High-performance 32-bit RISC architecture
– High-density 16-bit instruction set
– Leader in MIPS/Watt
– Embedded ICE In Circuit Emulation
• 4K bytes internal RAM
• Fully programmable External Bus Interface (EBI)
– Maximum external address space of 64M bytes
– Up to eight chip selects
– Software programmable 8/16-bit external databus
• Eight-level priority, individually maskable, vectored interrupt controller
– Four External interrupts, including a high priority low latency interrupt request
• 32 Programmable I/O lines
• Three-channel 16-bit timer/counter
– Three external clock inputs
– Two multi-purpose I/O pins per channel
• Two USARTs
– Two dedicated Peripheral Data Controller (PDC) channels per USART
• Programmable watchdog timer
• Low-power idle and power-down modes
• Fully static operation: 0 Hz to 33 MHz
• 2.7V to 3.6V operating range
• Available in a 100-lead TQFP package
Description
The AT91M40400 is a member of the Atmel AT91 16/32-bit Microcontroller family
which is based on the ARM7TDMI embedded processor. This processor has a high-
performance 32-bit RISC architecture with a high-density 16-bit instruction set and
very low power consumption. In addition, a large number of internally banked registers
result in very fast exception handling, making the device ideal for real-time control
applications. The AT91 ARM-based MCU family also features Atmel’s high-density,
nonvolatile memory technology. The on-chip Flash program memory is in-system pro-
grammable.
The AT91M40400 has a direct connection to off-chip memory, including Flash,
through the External Bus Interface.
The device is manufactured using Atmel’s high-density CMOS technology. By com-
bining the ARM7TDMI microcontroller core with an on-chip RAM and a wide range of
peripheral functions on a monolithic chip, the Atmel AT91M40400 is a powerful micro-
controller that provides a flexible, cost-effective solution to many compute-intensive
embedded control applications.
16/32-Bit
Microcontroller
AT91M40400
Summary
Full datasheet (lit# 0768B)
also available by e-mailing
Rev. 0768BS–08/98
1
1 page  
AT91M40400
Architectural Overview
The AT91M40400 architecture consists of two main buses,
the Advanced System Bus (ASB) and the Advanced
Peripheral Bus (APB). The ASB is designed for maximum
performance. It interfaces the processor with the on-chip
32-bit memories and the external memories and devices by
means of the External Bus Interface (EBI). The APB is
designed for accesses to on-chip peripherals and is opti-
mized for low power consumption. The AMBA Bridge pro-
vides an interface between the ASB and the APB.
An on-chip Peripheral Data Controller (PDC) transfers data
between the on-chip USARTs and the on and off-chip
memories without processor intervention. Most importantly,
the PDC removes the processor interrupt handling over-
head and significantly reduces the number of clock cycles
required for a data transfer. It can transfer up to 64k contig-
uous bytes without reprogramming the starting address. As
a result, the performance of the microcontroller is
increased and the power consumption reduced.
The AT91M40400 peripherals are designed to be pro-
grammed with a minimum number of instructions. Each
peripheral has a 16K byte address space allocated in the
upper 3M bytes of the 4G byte address space. Except for
the interrupt controller, the peripheral base address is the
lowest address of its memory space. The peripheral regis-
ter set is composed of control, mode, data, status and inter-
rupt registers.
To maximize the efficiency of bit manipulation, frequently
written registers are mapped into three memory locations.
The first address is used to set the individual register bits,
the second resets the bits and the third address reads the
value stored in the register. A bit can be set or reset by writ-
ing a one to the corresponding position at the appropriate
address. Writing a zero has no effect. Individual bits can
thus be modified without having to use costly read-modify-
write and complex bit manipulation instructions.
All of the external signals of the on-chip peripherals are
under the control of the Parallel I/O controller. The PIO
controller can be programmed to insert an input filter on
each pin or generate an interrupt on a signal change. After
reset, the user must carefully program the PIO Controller in
order to define which peripheral signals are connected with
off-chip logic.
The ARM7TDMI processor operates in little-endian mode
in the AT91M40400 microcontroller. The processor’s inter-
nal architecture and the ARM and Thumb instruction sets
are described in the ARM7TDMI Datasheet. The on-chip
peripherals are described in the subsequent sections of
this datasheet. Electrical characteristics are documented in
a separate datasheet entitled “AT91M40400 Electrical and
Mechanical Characteristics”.
The ARM Standard In-Circuit-Emulation debug interface is
supported via the ICE port of the AT91M40400 microcon-
troller. (This is not a standard IEEE 1149.1 JTAG Boundary
Scan interface)
PDC: Peripheral Data Controller
The AT91M40400 has a 4-channel PDC dedicated to the
two on-chip USARTs. One PDC channel is connected to
the receiving channel and one to the transmitting channel
of each USART.
The user interface of a PDC channel is integrated in the
memory space of each USART channel. It contains a 32-bit
address pointer register (US_RPR or US_TPR) and a 16-
bit byte count register (US_RCR or US_TCR). When the
programmed number of bytes are transferred, an end of
transfer interrupt is generated by the corresponding
USART.
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| PDF Descargar | [ Datasheet AT91M40400.PDF ] | |
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