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PDF AT91M42800A-33CI Data sheet ( Hoja de datos )
| Número de pieza | AT91M42800A-33CI | |
| Descripción | AT91 ARM Thumb Microcontrollers | |
| Fabricantes | ATMEL Corporation | |
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Features
• Utilizes the ARM7TDMI™ ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– Embedded ICE (In-circuit Emulation)
• 8K Bytes Internal SRAM
• Fully Programmable External Bus Interface (EBI)
– Maximum External Address Space of 64M Bytes
– Up to 8 Chip Selects
– Software Programmable 8/16-bit External Data Bus
• 8-channel Peripheral Data Controller
• 8-level Priority, Individually Maskable, Vectored Interrupt Controller
– 5 External Interrupts, Including a High-priority, Low-latency Interrupt Request
• 54 Programmable I/O Lines
• 6-channel 16-bit Timer/Counter
– 6 External Clock Inputs, 2 Multi-purpose I/O Pins per Channel
• 2 USARTs
– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART
– Support for up to 9-bit Data Transfers
• 2 Master/Slave SPI Interfaces
– 2 Dedicated Peripheral Data Controller (PDC) Channels per SPI
– 8- to 16-bit Programmable Data Length
– 4 External Slave Chip Selects per SPI
• 3 System Timers:
– Period Interval Timer (PIT); Real-time Timer (RTT); Watchdog Timer (WDT)
• Power Management Controller (PMC)
– CPU and Peripherals Can be Deactivated Individually
• Clock Generator with 32.768 kHz Low-power Oscillator and PLL
– Support for 38.4 kHz Crystals
– Software Programmable System Clock (up to 33 MHz)
• IEEE 1149.1 JTAG Boundary Scan on All Active Pins
• Fully Static Operation: 0 Hz to 33 MHz Internal Frequency Range
at VDDCORE = 3.0V, 85°C
• 2.7V to 3.6V Core and PLL Operating Voltage Range; 2.7V to 5.5V I/O Operating Voltage
Range
• -40°C to +85°C Temperature Range
• Available in a 144-lead TQFP Package and in 144-ball BGA Package
AT91
ARM® Thumb®
Microcontrollers
AT91M42800A
Summary
Description
The AT91M42800A is a member of the Atmel AT91 16/32-bit microcontroller family,
which is based on the ARM7TDMI processor core. This processor has a high-perfor-
mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low
power consumption. In addition, a large number of internally banked registers result in
very fast exception handling, making the device ideal for real-time control applications.
The AT91 ARM-based MCU family also features Atmel’s high-density, in-system pro-
grammable, nonvolatile memor y technology. The AT91M42800A has a direct
connection to off-chip memory, including Flash, through the External Bus Interface.
The Power Management Controller allows the user to adjust device activity according
to system requirements, and, with the 32.768 kHz low-power oscillator, enables the
AT91M42800A to reduce power requirements to an absolute minimum. The
AT91M42800A is manufactured using Atmel’s high-density CMOS technology. By
combining the ARM7TDMI processor core with on-chip SRAM and a wide range of
peripheral functions including timers, serial communication controllers and a versatile
clock generator on a monolithic chip, the AT91M42800A provides a highly-flexible and
cost-effective solution to many compute-intensive applications.
Rev. 1779BS–ATARM–02/02
Note: This is a summary document. A complete document is 1
available on our web site at www.atmel.com.
1 page  
AT91M42800A
Pin Description
Table 3. AT91M42800A Pin Description
Module
EBI
AIC
TC
USART
SPIA
SPIB
PIO
ST
CLOCK
Test and
Reset
Name
A0 - A23
D0 - D15
CS4 - CS7
NCS0 - NCS3
NWR0
NWR1
NRD
NWE
NOE
NUB
NLB
NWAIT
BMS
PME
IRQ0 - IRQ3
FIQ
TCLK0 - TCLK5
TIOA0 - TIOA5
TIOB0 - TIOB5
SCK0 - SCK1
TXD0 - TXD1
RXD0 - RXD1
SPCKA/SPCKB
MISOA/MISOB
MOSIA/MOSIB
NSSA/NSSB
NPCSA0 - NPCSA3
NPCSB0 - NPCSB3
PA0 - PA29
PB0 - PB23
NWDOVF
XIN
XOUT
PLLRCA
PLLRCB
MCKO
NRST
MODE0 - MODE1
Function
Address Bus
Data Bus
Chip Select
Chip Select
Lower Byte 0 Write Signal
Lower Byte 1 Write Signal
Read Signal
Write Enable
Output Enable
Upper Byte Select (16-bit SRAM)
Lower Byte Select (16-bit SRAM)
Wait Input
Boot Mode Select
Protect Mode Enable
External Interrupt Request
Fast External Interrupt Request
Timer External Clock
Multi-purpose Timer I/O Pin A
Multi-purpose Timer I/O Pin B
External Serial Clock
Transmit Data Output
Receive Data Input
Clock
Master In Slave Out
Master Out Slave In
Slave Select
Peripheral Chip Selects
Programmable I/O Port A
Programmable I/O Port B
Watchdog Timer Overflow
Oscillator Input or External Clock
Oscillator Output
RC Filter for PLL A
RC Filter for PLL B
Clock Output
Hardware Reset Input
Mode Selection
Type
Output
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
I/O
I/O
I/O
Output
Input
I/O
I/O
I/O
Input
Active
Level
–
–
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
–
High
–
–
–
–
–
–
–
–
–
–
–
Low
Comments
All valid after reset
A23 - A20 after reset
Used in Byte Write option
Used in Byte Write option
Used in Byte Write option
Used in Byte Select option
Used in Byte Select option
Used in Byte Select option
Used in Byte Select option
Sampled during reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
Output Low
PIO-controlled after reset
I/O
I/O
Output
Input
Output
Input
Input
Output
Input
Input
– Input after reset
– Input after reset
Low Open drain
–
–
–
–
–
Low Schmitt trigger
–
1779BS–ATARM–02/02
5
5 Page 
AT91M42800A
Product Overview
Power Supply
The AT91M42800A has three kinds of power supply pins:
• VDDCORE pins, which power the chip core
• VDDIO pins, which power the I/O lines
• VDDPLL pins, which power the oscillator and PLL cells
VDDCORE and VDDIO pins allow core power consumption to be reduced by supplying it with
a lower voltage than the I/O lines. The VDDCORE pins must never be powered at a voltage
greater than the supply voltage applied to the VDDIO.
The VDDPLL pin is used to supply the oscillator and both PLLs. The voltage applied on these
pins is typically 3.3V, and it must not be lower than VDDCORE.
Typical supported voltage combinations are shown in the following table:
Pins
VDDCORE
VDDIO
VDDPLL
Nominal Supply Voltages
3.3V
3.0V or 3.3V
5.0V
3.0V or 3.3V
3.3V
3.0V or 3.3V
Input/Output
Considerations
Operating Modes
After the reset, the peripheral I/Os are initialized as inputs to provide the user with maximum
flexibility. It is recommended that in any application phase, the inputs to the AT91M42800A
microcontroller be held at valid logic levels to minimize the power consumption.
The AT91M42800A has two pins dedicated to defining MODE0 and MODE1 operating modes.
These pins allow the user to enter the device in Boundary Scan mode. They also allow the
user to run the processor from the on-chip oscillator and from an external clock by bypassing
the on-chip oscillator. The last mode is reserved for test purposes. A chip reset must be per-
formed (NRST and NTRST) after MODE0 and/or MODE1 have been changed.
MODE0
0
0
1
1
MODE1
0
1
0
1
Operating Mode
Normal operating mode by using the on-chip oscillator
Boundary Scan Mode
Normal operating mode by using an external clock on XIN
Reserved for test
Clock Generator
The AT91M42800A microcontroller embeds a 32.768 kHz oscillator that generates the Slow
Clock (SLCK). This on-chip oscillator can be bypassed by setting the correct logical level on
MODE0 and MODE1 pins, as shown above. In this case, SLCK equals XIN.
The AT91M42800A microcontroller has a fully static design and works either on the Master
Clock (MCK), generated from the Slow Clock by means of the two integrated PLLs, or on the
Slow Clock (SLCK).
These clocks are also provided as an output of the device on the pin MCKO, which is multi-
plexed with a general-purpose I/O line. While NRST is active, and after the reset, the MCKO is
valid and outputs an image of the SLCK signal. The PIO Controller must be programmed to
use this pin as standard I/O line.
1779BS–ATARM–02/02
11
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