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PDF AT29LV512-25TC Data sheet ( Hoja de datos )
| Número de pieza | AT29LV512-25TC | |
| Descripción | 512K 64K x 8 3-volt Only CMOS Flash Memory | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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AT29LV512
Features
Single Supply Voltage, Range 3V to 3.6V
• 3-Volt-Only Read and Write Operation
• Software Protected Programming
•• Low Power Dissipation
15 mA Active Current
20 µA CMOS Standby Current
Fast Read Access Time - 200 ns
•• Sector Program Operation
Single Cycle Reprogram (Erase and Program)
512 Sectors (128 bytes/sector)
Internal Address and Data Latches for 128-Bytes
Fast Sector Program Cycle Time - 20 ms Max.
• Internal Program Control and Timer
• DATA Polling for End of Program Detection
• Typical Endurance > 10,000 Cycles
• CMOS and TTL Compatible Inputs and Outputs
•• Commercial and Industrial Temperature Ranges
Description
The AT29LV512 is a 3-volt-only in-system Flash programmable erasable read only
memory (PEROM). Its 512K of memory is organized as 65,536 words by 8 bits. Manu-
factured with Atmel’s advanced nonvolatile CMOS technology, the device offers ac-
cess times to 200 ns with power dissipation of just 54 mW over the commercial tem-
perature range. When the device is deselected, the CMOS standby current is less
than 20 µA. The device endurance is such that any sector can typically be written to
in excess of 10,000 times.
(continued)
512K (64K x 8)
3-volt Only
CMOS Flash
Memory
Pin Configurations
Pin Name Function
A0 - A15 Addresses
CE Chip Enable
OE Output Enable
WE Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
PLCC Top View
AT29LV512
TSOP Top View
Type 1
0177I
4-43
1 page  
AT29LV512
AC Read Characteristics
Symbol
tACC
tCE (1)
tOE (2)
tDF (3, 4)
tOH
Parameter
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
Output Hold from OE, CE or
Address, whichever occurred first
AC Read Waveforms (1, 2, 3, 4)
AT29LV512-15
Min Max
150
150
0 70
0 40
0
AT29LV512-20
Min Max
200
200
0 100
0 50
0
AT29LV512-25
Min Max
250
250
0 120
0 60
0
Units
ns
ns
ns
ns
ns
Notes: 1. CE may be delayed up to tACC - tCE after the address
transition without impact on tACC .
2. OE may be delayed up to tCE - tOE after the falling
edge of CE without impact on tCE or by tACC - tOE
after an address change without impact on tACC .
3. tDF is specified from OE or CE whichever occurs first
(CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance (f = 1 MHz, T = 25°C) (1)
Typ Max
CIN 4 6
COUT
8 12
Note: 1. These parameters are characterized and not 100% tested.
Units
pF
pF
Conditions
VIN = 0V
VOUT = 0V
4-47
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet AT29LV512-25TC.PDF ] | |
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