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PDF AT43101 Data sheet ( Hoja de datos )
| Número de pieza | AT43101 | |
| Descripción | PCMCIA Card Memory Interface Circuit with 256 Bytes of Internal Attribute Memory EEPROM | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
Supports PCMCIA PC Card Standard - Release 2.1
• Directly connects to PCMCIA Connector
• No Additional Circuits Required
•• 256 x 8 Internal Parallel E2PROM for CIS
Endurance: 10,000 Write Cycles
Data Retention: 10 Years
Internally Controlled Write Algorithm
Operates over VCC = 4.5 to 5.5 Volts
• 64 Pin TQFP, Max. Height = 1.2 mm Mounted
• Usage is Two Devices Per Card
• Dual Mode Device with Mode Select Pin
•• Supports Up to 64 Mbytes of:
Flash
E2PROM
SRAM
ROM
OTP
Description
The AT43101 is a low power, high integration PCMCIA interface chip set for memory
cards. It provides a complete PCMCIA PC Card Standard Release 2.1 compliant inter-
face with no other support devices. Two AT43101’s are used on each memory card.
A mode select pin configures the device for operation as a low order address and data
buffer when low and as the high order address buffer/decoder when high. The two
devices together form a complete address and data buffer, address decoder, memory
device selection logic, read and write control logic and a Card Information Structure
(CIS). Eight chip enable outputs are provided, supporting 16 memory devices. The
device is pinned out for direct connection to the PCMCIA connector without PC trace
cross-overs. Its 1.0 mm thick body allows population of both sides of a Type 1
PCMCIA card.
PCMCIA Card
Memory
Interface
Circuit with
256 Bytes of
Internal
Attribute
Memory
EEPROM
AT43101
OE*
D1
D9
D2
D10
D3
D11
VSS
D4
D12
D5
D13
D6
D14
D7
D15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AT43101
MODE A
48 A8
A10 1
47 ID1
A11 2
46 ID9
A17 3
45 ID2
A18 4
44 ID10 A19 5
43 ID3
A20 6
42 ID11 A21 7
41 VSS VSS 8
40 ID4 SEL0
9
39 ID12 A9 10
38 ID5
A13 11
37 ID13 A14 12
36 ID6
A16 13
35 ID14 A15 14
34 ID7
A12 15
33 ID15 A22 16
AT43101
MODE B
48 IA10
47 IA11
46 IA17
45 IA18
44 IA19
43 IA20
42 IA21
41 VSS
40 Reset
39 IA9
38 IA13
37 IA14
36 IA16
35 IA15
34 IA12
33 IA22
1 page  
AT43101
Address Decoder Operation
SGL/DBL* = H
SEL[1:0]
DEC[2:0]
ICE[7:0]*
XX LLL HHHHHHHL
XX LLH HHHHHHLH
XX LHL HHHHHLHH
XX
LHH
HHHHLHHH
XX HLL HHHLHHHH
XX
HLH
HHLHHHHH
XX
HHL
HLHHHHHH
XX
HHH
LHHHHHHH
SEL[1:0]
LL
LL
LL
LL
LH
HL
HH
SGL/DBL* = L
DEC[2:0]
XLL
XLH
XHL
XHH
ICE[7:0]*
HHHHHHHL
HHHHHHLH
HHHHHLHH
HHHHLHHH
XXX
XXX
XXX
HHLHHHHH
HLHHHHHH
LHHHHHHH
The AT43101 provides separate output and write enables for
the upper and lower bytes of the memory array to implement
byte addressing. The assertion of these outputs under the
control of A0, CE2*, CE1*, OE* and WE* is given by the
following table when REG* is high.
Byte Control Logic Operation
OE*
WE*
CE2*
CE1*
A0
IOEL*
IOEH*
IWEL*
IWEH*
HHXXXHHHH
L HHHXHHHH
LHHL L LHHH
L HH L HH L HH
L H L HXH L HH
LHL L X L LHH
H L HHXHHHH
HLHL LHHLH
H L H L HHHH L
HL LHXHHHL
HL L L XHHL L
The IWP* input provides write protection for common
memory. When IWP* is low, assertion of IWEL* and
IWEH* is inhibited. The WPATT input provides write pro-
tection for the attribute memory when high. This signal is
pulled down internally for applications not requiring write
protection. In addition, the AT43101 is disabled for 3 milli-
seconds during power up to prevent writes from occurring
to either attribute or common memory. The state of the
A*/B pin is also latched at this time. The AT43101 does
not support the optional PCMCIA WAIT* signal.
5
5 Page 
AT43101
AC Read Waveforms
A[24:0], SGL/DBL*,
DEC[2:0], SEL[1:0]
tia(A)
ADDRESS VALID
tv(A)
IA[24:0]
tice(A)
ICE[7:0]*
tice(REG)
tda(A)
tice(CE)
tioeh(AO)
REG*
ten(REG)
tdis(REG)
CE1*, CE2*
OE*
D[15:0]
HIGH Z
ten(CE)
ten(OE)
tdis(CE)
tdis(OE)
DATA VALID
IOEH*,
IOEL*
ID[15:0]
tioel(CE)
tioel(OE)
tioel(REG)
tioel(A0)
tioeh(OE)
tioeh(REG)
tioeh(CE)
td(ID)
DATA VALID
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet AT43101.PDF ] | |
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