AT45DB Datasheet PDF - ATMEL Corporation
| Part Number | AT45DB | |
| Description | 1-Megabit 2.7-volt Only Serial DataFlash | |
| Manufacturers | ATMEL Corporation | |
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Features
• Single 2.7V - 3.6V Supply
• Serial Interface Architecture
• Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– 512 Pages (264 Bytes/Page) Main Memory
• Optional Page and Block Erase Operations
• One 264-Byte SRAM Data Buffer
• Internal Program and Control Timer
• Fast Page Program Time – 7 ms Typical
• 120 µs Typical Page to Buffer Transfer Time
• Low-Power Dissipation
– 4 mA Active Read Current Typical
– 2 µA CMOS Standby Current Typical
• 13 MHz Max Clock Frequency
• Hardware Data Protection Feature
• Serial Peripheral Interface (SPI) Compatible – Modes 0 and 3
• CMOS and TTL Compatible Inputs and Outputs
• Commercial and Industrial Temperature Ranges
Description
The AT45DB011 is a 2.7-volt only, serial interface Flash memory suitable for in-sys-
tem reprogramming. Its 1,081,344 bits of memory are organized as 512 pages of 264
bytes each. In addition to the main memory, the AT45DB011 also contains one SRAM
data buffer of 264 bytes. Unlike conventional Flash memories that are accessed ran-
domly with multiple address lines and a parallel interface, the DataFlash uses a serial
interface to sequentially access its data. The simple serial interface facilitates hard-
(continued)
Pin Configurations
SOIC
Pin Name
CS
SCK
SI
Function
Chip Select
Serial Clock
Serial Input
SI
SCK
RESET
CS
1
2
3
4
8 SO
7 GND
6 VCC
5 WP
SO Serial Output
WP
Hardware Page
Write Protect Pin
RESET
Chip Reset
RDY/BUSY Ready/Busy
PLCC
TSSOP Top View
Type 1
SCK
SI
SO
NC
NC
NC
NC
NC
NC
5
6
7
8
9
10
11
12
13
29 WP
28 RESET
27 RDY/BUSY
26 NC
25 NC
24 NC
23 NC
22 NC
21 NC
RDY/BUSY
RESET
WP
VCC
GND
SCK
SO
1
2
3
4
5
6
7
14 CS
13 NC
12 NC
11 NC
10 NC
9 NC
8 SI
Note: PLCC package pins 16
and 17 are DON’T CONNECT
1-Megabit
2.7-volt Only
Serial
DataFlash®
AT45DB011
Preliminary
AT45DB011
Preliminary 16-
Megabit 2.7-volt
Only Serial
DataFlash
Rev. 1103C–08/98
1
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AT45DB011
Block Erase Addressing
PA8 PA7 PA6 PA5 PA4
00000
00000
00001
00001
•••••
•••••
•••••
11110
11110
11111
11111
MAIN MEMORY PAGE PROGRAM: This operation is a
combination of the Buffer Write and Buffer to Main Memory
Page Program with Built-In Erase operations. Data is first
shifted into the buffer from the SI pin and then programmed
into a specified page in the main memory. An 8-bit opcode
of 82H is followed by the six reserved bits and 18 address
bits. The nine most significant address bits (PA8-PA0)
select the page in the main memory where data is to be
written, and the next nine address bits (BFA8-BFA0) select
the first byte in the buffer to be written. After all address bits
are shifted in, the part will take data from the SI pin and
store it in the data buffer. If the end of the buffer is reached,
the device will wrap around back to the beginning of the
buffer. When there is a low to high transition on the CS pin,
the part will first erase the selected page in main memory to
all 1s and then program the data stored in the buffer into
the specified page in the main memory. Both the erase and
the programming of the page are internally self timed and
should take place in a maximum of time tEP. During this
time, the status register will indicate that the part is busy.
AUTO PAGE REWRITE: This mode is only needed if multi-
ple bytes within a page or multiple pages of data are modi-
fied in a random fashion. This mode is a combination of two
operations: Main Memory Page to Buffer Transfer and
Buffer to Main Memory Page Program with Built-In Erase.
A page of data is first transferred from the main memory to
the data buffer, and then the same data (from the buffer) is
programmed back into its original page of main memory.
An 8-bit opcode of 58H is followed by the six reserved bits,
nine address bits (PA8-PA0) that specify the page in main
memory to be rewritten, and nine additional don’t care bits.
When a low to high transition occurs on the CS pin, the part
will first transfer data from the page in main memory to the
buffer and then program the data from the buffer back into
same page of main memory. The operation is internally
PA3 PA2 PA1 PA0 Block
0XXX0
1XXX1
0XXX2
1XXX3
•••••
•••••
•••••
0 X X X 60
1 X X X 61
0 X X X 62
1 X X X 63
self-timed and should take place in a maximum time of tEP.
During this time, the status register will indicate that the
part is busy.
If a sector is programmed or reprogrammed sequentially
page by page, then the programming algorithm shown in
Figure 1 is recommended. Otherwise, if multiple bytes in a
page or several pages are programmed randomly in a sec-
tor, then the programming algorithm shown in Figure 2 is
recommended.
STATUS REGISTER: The status register can be used to
determine the device’s ready/busy status, the result of a
Main Memory Page to Buffer Compare operation, or the
device density. To read the status register, an opcode of
57H must be loaded into the device. After the last bit of the
opcode is shifted in, the eight bits of the status register,
starting with the MSB (bit 7), will be shifted out on the SO
pin during the next eight clock cycles. The five most-signifi-
cant bits of the status register will contain device informa-
tion, while the remaining three least-significant bits are
reserved for future use and will have undefined values.
After bit 0 of the status register has been shifted out, the
sequence will repeat itself (as long as CS remains low and
SCK is being toggled) starting again with bit 7. The data in
the status register is constantly updated, so each repeating
sequence will output new data.
Ready/busy status is indicated using bit 7 of the status reg-
ister. If bit 7 is a 1, then the device is not busy and is ready
to accept the next command. If bit 7 is a 0, then the device
is in a busy state. The user can continuously poll bit 7 of the
status register by stopping SCK once bit 7 has been output.
The status of bit 7 will continue to be output on the SO pin,
and once the device is no longer busy, the state of SO will
change from 0 to 1. There are eight operations which can
cause the device to be in a busy state: Main Memory Page
to Buffer Transfer, Main Memory Page to Buffer Compare,
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for AT45DB electronic component. |
| Information | Total 19 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ AT45DB.PDF Datasheet ] | |
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