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PDF AT45DB321 Data sheet ( Hoja de datos )
| Número de pieza | AT45DB321 | |
| Descripción | 32-Megabit 2.7-volt Only Serial DataFlash | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Single 2.7V - 3.6V Supply
• Serial Interface Architecture
• Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– 8192 Pages (528 Bytes/Page) Main Memory
• Optional Page and Block Erase Operations
• Two 528-Byte SRAM Data Buffers – Allows Receiving of Data while Reprogramming of
Nonvolatile Memory
• Internal Program and Control Timer
• Fast Page Program Time – 7 ms Typical
• 120 µs Typical Page to Buffer Transfer Time
• Low-Power Dissipation
– 4 mA Active Read Current Typical
– 3 µA CMOS Standby Current Typical
• 13 MHz Max Clock Frequency
• Hardware Data Protection Feature
• Serial Peripheral Interface (SPI) Compatible – Modes 0 and 3
• CMOS and TTL Compatible Inputs and Outputs
• Commercial and Industrial Temperature Ranges
Description
The AT45DB321 is a 2.7-volt only, serial interface Flash memory suitable for in-sys-
tem reprogramming. Its 34,603,008 bits of memory are organized as 8192 pages of
528 bytes each. In addition to the main memory, the AT45DB321 also contains two
SRAM data buffers of 528 bytes each. The buffers allow receiving of data while a
page in the main memory is being reprogrammed. Unlike conventional Flash memo-
(continued)
Pin Configurations
CBGA Top View Through Package
Pin Name Function
12345
CS
SCK
SI
SO
WP
Chip Select
Serial Clock
Serial Input
Serial Output
Hardware Page
Write Protect Pin
A
NC NC NC NC
B
NC SCK GND VCC NC
C
NC CS RDY/BSY WP NC
D
NC SO SI RESET NC
E
NC NC NC NC NC
RESET
Chip Reset
RDY/BUSY Ready/Busy
TSOP Top View
Type 1
RDY/BUSY
RESET
WP
NC
NC
NC
VCC
GND
NC
NC
NC
NC
CS
SCK
SI
SO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 NC
31 NC
30 NC
29 NC
28 NC
27 NC
26 NC
25 NC
24 NC
23 NC
22 NC
21 NC
20 NC
19 NC
18 NC
17 NC
32-Megabit
2.7-volt Only
Serial
DataFlash®
AT45DB321
Preliminary
AT45DB321
Preliminary 16-
Megabit 2.7-volt
Only Serial
DataFlash
Rev. 1121A–09/98
1
1 page  
AT45DB321
Block Erase Addressing
PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Block
0 0 0 0 0 0 0 0 0 0XXX 0
0 0 0 0 0 0 0 0 0 1XXX 1
0 0 0 0 0 0 0 0 1 0XXX 2
0 0 0 0 0 0 0 0 1 1XXX 3
• • • •••••••••• •
• • • •••••••••• •
• • • •••••••••• •
1 1 1 1 1 1 1 1 0 0 X X X 1020
1 1 1 1 1 1 1 1 0 1 X X X 1021
1 1 1 1 1 1 1 1 1 0 X X X 1022
1 1 1 1 1 1 1 1 1 1 X X X 1023
MAIN MEMORY PAGE PROGRAM: This operation is a
combination of the Buffer Write and Buffer to Main Memory
Page Program with Built-In Erase operations. Data is first
shifted into buffer 1 or buffer 2 from the SI pin and then pro-
grammed into a specified page in the main memory. An 8-
bit opcode, 82H for buffer 1 or 85H for buffer 2, is followed
by one reserved bit and 23 address bits. The 13 most sig-
nificant address bits (PA12-PA0) select the page in the
main memory where data is to be written, and the next 10
address bits (BFA9-BFA0) select the first byte in the buffer
to be written. After all address bits are shifted in, the part
will take data from the SI pin and store it in one of the data
buffers. If the end of the buffer is reached, the device will
wrap around back to the beginning of the buffer. When
there is a low to high transition on the CS pin, the part will
first erase the selected page in main memory to all 1s and
then program the data stored in the buffer into the specified
page in the main memory. Both the erase and the program-
ming of the page are internally self timed and should take
place in a maximum of time tEP. During this time, the status
register will indicate that the part is busy.
AUTO PAGE REWRITE: This mode is only needed if multi-
ple bytes within a page or multiple pages of data are modi-
fied in a random fashion. This mode is a combination of two
operations: Main Memory Page to Buffer Transfer and
Buffer to Main Memory Page Program with Built-In Erase.
A page of data is first transferred from the main memory to
buffer 1 or buffer 2, and then the same data (from buffer 1
or buffer 2) is programmed back into its original page of
main memory. An 8-bit opcode, 58H for buffer 1 or 59H for
buffer 2, is followed by one reserved bit, 13 address bits
(PA12-PA0) that specify the page in main memory to be
rewritten, and 10 additional don't care bits. When a low to
high transition occurs on the CS pin, the part will first trans-
fer data from the page in main memory to a buffer and then
program the data from the buffer back into same page of
main memory. The operation is internally self-timed and
should take place in a maximum time of tEP. During this
time, the status register will indicate that the part is busy.
If a sector is programmed or reprogrammed sequentially
page by page, then the programming algorithm shown in
Figure 1 is recommended. Otherwise, if multiple bytes in a
page or several pages are programmed randomly in a sec-
tor, then the programming algorithm shown in Figure 2 is
recommended.
STATUS REGISTER: The status register can be used to
determine the device’s ready/busy status, the result of a
Main Memory Page to Buffer Compare operation, or the
device density. To read the status register, an opcode of
57H must be loaded into the device. After the last bit of the
opcode is shifted in, the eight bits of the status register,
starting with the MSB (bit 7), will be shifted out on the SO
pin during the next eight clock cycles. The five most-signifi-
cant bits of the status register will contain device informa-
tion, while the remaining three least-significant bits are
reserved for future use and will have undefined values.
After bit 0 of the status register has been shifted out, the
sequence will repeat itself (as long as CS remains low and
SCK is being toggled) starting again with bit 7. The data in
the status register is constantly updated, so each repeating
sequence will output new data.
Ready/busy status is indicated using bit 7 of the status reg-
ister. If bit 7 is a 1, then the device is not busy and is ready
to accept the next command. If bit 7 is a 0, then the device
is in a busy state. The user can continuously poll bit 7 of the
status register by stopping SCK once bit 7 has been output.
The status of bit 7 will continue to be output on the SO pin,
and once the device is no longer busy, the state of SO will
change from 0 to 1. There are eight operations which can
5
5 Page 
AT45DB321
Write Operations
The following block diagram and waveforms illustrate the various write sequences available.
FLASH MEMORY ARRAY
PAGE (528 BYTES)
BUFFER 1 TO
MAIN MEMORY
PAGE PROGRAM
BUFFER 1 (528 BYTES)
BUFFER 1
WRITE
MAIN MEMORY
PAGE PROGRAM
THROUGH BUFFER 2
MAIN MEMORY PAGE
PROGRAM THROUGH
BUFFER 1
I/O INTERFACE
BUFFER 2 TO
MAIN MEMORY
PAGE PROGRAM
BUFFER 2 (528 BYTES)
BUFFER 2
WRITE
SI
Main Memory Page Program through Buffers
CS
SI CMD
Buffer Write
r , PA12-6 PA5-0, BFA9-8 BFA7-0
n
CS
SI
CMD
X X···X, BFA9-8 BFA7-0
n
· Completes writing into selected buffer
· Starts self-timed erase/program operation
n+1 Last Byte
· Completes writing into selected buffer
n+1 Last Byte
Buffer to Main Memory Page Program
(Data from Buffer Programmed into Flash Page)
Starts self-timed erase/program operation
CS
SI
CMD
r , PA12-6
PA5-0, XX
X
Each transition represents
8 bits and 8 clock cycles
n = 1st byte written
n+1 = 2nd byte written
11
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| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AT45DB321.PDF ] | |
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