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PDF AT48801-16QI Data sheet ( Hoja de datos )
| Número de pieza | AT48801-16QI | |
| Descripción | 8 Bit Spread- Spectrum Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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AT48801
Features
Compatible with MCS-51™ Products
• 8K bytes of On-Board Program Memory
• Fully Static Operation: 0 Hz to 16 MHz
• 256 x 8 Bit Internal RAM
• 32 Programmable I/O Lines
• Three 16 Bit Timer/Counters
• Eight Interrupt Sources
• Programmable Serial Channel
•• Low Power Idle and Power Down Modes
Description
The AT48801 is a low-power, high-performance CMOS 8 bit microcomputer with 8K
bytes on-board program memory. The device is compatible with the industry standard
80C51 and 80C52 instruction set and pinout. The Atmel AT48801 is a powerful micro-
computer which provides a highly flexible and cost effective solution to spread-spec-
trum applications.
The AT48801 provides the following standard features: 8K bytes of program memory,
256-bytes of RAM, 32 I/O lines, three 16 bit timer/counters, a six-vector two-level
interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In
addition, the AT48801 is designed with static logic for operation down to zero fre-
quency and supports two software selectable power saving modes. The Idle Mode
stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt sys-
tem to continue functioning. The Power Down Mode saves the RAM contents but
freezes the oscillator, disabling all other chip functions until the next hardware reset.
8 Bit
Spread-
Spectrum
Microcontroller
Preliminary
Pin Configuration
PQFP
0629A
1-1
1 page  
AT48801
Table 2. T2CON—Timer/Counter 2 Control Register
T2CON Address = 0C8H
Bit Addressable
TF2 EXF2
Bit 7
6
RCLK
5
TCLK
4
Reset Value = 0000 0000B
EXEN2
3
TR2
2
C/T2
1
CP/RL2
0
Symbol
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
Function
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be
set when either RCLK = 1 or TCLK = 1.
Timer 2 external flag set when either a capture or reload is caused by a negative transition on
T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector
to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an
interrupt in up/down counter mode (DCEN = 1).
Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its
receive clock in serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the
receive clock.
Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its
transmit clock in serial port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for
the transmit clock.
Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative
transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer
2 to ignore events at T2EX.
Start/Stop control for Timer 2. TR2 = 1 starts the timer.
Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event
counter (falling edge triggered).
Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if
EXEN2 = 1. CP/RL2 = 0 causes automatic reloads to occur when Timer 2 overflows or negative
transitions occur at T2EX when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored
and the timer is forced to auto-reload on Timer 2 overflow.
Special Function Registers (Continued)
(RCAP2H, RCAP2L) are the Capture/Reload registers for
Timer 2 in 16 bit capture mode or 16 bit auto-reload mode.
Interrupt Registers The individual interrupt enable bits
are in the IE register. Two priorities can be set for each of
the six interrupt sources in the IP register.
Data Memory
The AT48801 implements 256-bytes of on-chip RAM. The
upper 128-bytes occupy a parallel address space to the
Special Function Registers. That means the upper 128-
bytes have the same addresses as the SFR space but are
physically separate from SFR space.
When an instruction accesses an internal location above
address 7FH, the address mode used in the instruction
specifies whether the CPU accesses the upper 128-bytes
of RAM or the SFR space. Instructions that use direct ad-
dressing access SFR space.
For example, the following direct addressing instruction
accesses the SFR at location 0A0H (which is P2).
MOV 0A0H, #data
Instructions that use indirect addressing access the upper
128-bytes of RAM. For example, the following indirect ad-
dressing instruction, where R0 contains 0A0H, accesses
the data byte at address 0A0H, rather than P2 (whose ad-
dress is 0A0H).
(continued)
1-5
5 Page 
AT48801
Interrupts (Continued)
to. In fact, the service routine may have to determine
whether it was TF2 or EXF2 that generated the interrupt,
and that bit will have to be cleared in software.
The Timer 0 and Timer 1 flags, TF0 and TFI, are set at
S5P2 of the cycle in which the timers overflow. The values
are then polled by the circuitry in the next cycle. However,
the Timer 2 flag, TF2, is set at S2P2 and is polled in the
same cycle in which the timer overflows.
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively,
of an inverting amplifier that can be configured for use as
an on-chip oscillator, as shown in Figure 7. Either a quartz
crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be
left unconnected while XTAL1 is driven, as shown in Fig-
ure 8. There are no requirements on the duty cycle of the
external clock signal, since the input to the internal clock-
ing circuitry is through a divide-by-two flip-flop, but mini-
mum and maximum voltage high and low time specifica-
tions must be observed.
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-
chip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and all the spe-
cial functions registers remain unchanged during this
mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
Note that when idle mode is terminated by a hardware re-
set, the device normally resumes program execution from
where it left off, up to two machine cycles before the inter-
nal reset algorithm takes control. On-chip hardware inhib-
its access to internal RAM in this event, but access to the
port pins is not inhibited. To eliminate the possibility of an
unexpected write to a port pin when idle mode is termi-
nated by a reset, the instruction following the one that in-
vokes idle mode should not write to a port pin or to external
memory.
Power Down Mode
In the power down mode, the oscillator is stopped, and the
instruction that invokes power down is the last instruction
executed. The on-chip RAM and Special Function Regis-
ters retain their values until the power down mode is termi-
nated. The only exit from power down is a hardware reset.
Reset redefines the SFRs but does not change the on-
chip RAM. The reset should not be activated before VCC
is restored to its normal operating level and must be held
active long enough to allow the oscillator to restart and
stabilize.
Figure 7. Oscillator Connections
Notes: C1, C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators
Figure 8. External Clock Drive Configuration
Status of External Pins During Idle and Power Down
Mode
Idle
Idle
Power Down
Power Down
Program Memory
Internal
External
Internal
External
ALE
1
1
0
0
PSEN
1
1
0
0
PORT0
Data
Float
Data
Float
PORT1
Data
Data
Data
Data
PORT2
Data
Address
Data
Data
PORT3
Data
Data
Data
Data
1-11
11 Page | ||
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| PDF Descargar | [ Datasheet AT48801-16QI.PDF ] | |
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