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PDF AT49BV004T-12TI Data sheet ( Hoja de datos )
| Número de pieza | AT49BV004T-12TI | |
| Descripción | 4-Megabit 512K x 8/ 256K x 16 CMOS Flash Memory | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• 2.7V to 3.6V Read/Write Operation
• Fast Read Access Time - 120 ns
• Internal Erase/Program Control
• Sector Architecture
– One 8K Words (16K bytes) Boot Block with Programming Lockout
– Two 4K Words (8K bytes) Parameter Blocks
– One 240K Words (480K bytes) Main Memory Array Block
• Fast Sector Erase Time - 10 seconds
• Byte-by-Byte or Word-By-Word Programming - 30 µs Typical
• Hardware Data Protection
• DATA Polling For End Of Program Detection
• Low-Power Dissipation
– 25 mA Active Current
– 50 µA CMOS Standby Current
• Typical 10,000 Write Cycles
Description
The AT49BV004(T) and AT49BV4096A(T) are 3-volt, 4-megabit Flash Memories
organized as 524,288 words of 8 bits each or 256K words of 16 bits each. Manufac-
tured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access
times to 120 ns with power dissipation of just 67 mW at 2.7V read. When deselected,
the CMOS standby current is less than 50 µA.
The device contains a user-enabled “boot block” protection feature. Two versions of
the feature are available: the AT49BV004/4096A locates the boot block at lowest
order addresses (“bottom boot”); the AT49BV004T/4096AT locates it at highest order
addresses (“top boot”).
To allow for simple in-system reprogrammability, the AT49BV004(T)/4096A(T) does
not require high input voltages for programming. Reading data out of the device is
similar to reading from an EPROM; it has standard CE, OE, and WE inputs to avoid
bus contention. Reprogramming the AT49BV004(T)/4096A(T) is performed by first
erasing a block of data and then programming on a byte-by-byte or word-by-word
basis.
Pin Configurations
(continued)
Pin Name
A0 - A18
CE
OE
WE
RESET
RDY/BUSY
VPP
I/O0 - I/O14
I/O15(A-1)
BYTE
NC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
Ready/Busy Output
Optional Power Supply for Faster
Program/Erase Operations
Data Inputs/Outputs
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
Selects Byte or Word Mode
No Connect
4-Megabit
(512K x 8/
256K x 16)
CMOS Flash
Memory
AT49BV004
AT49BV004T
AT49BV4096A
AT49BV4096AT
Preliminary
Rev. 1139A–09/98
1
1 page  
AT49BV004(T)/4096A(T)
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT49BV004(T)/4096A(T) features
DATA polling to indicate the end of a program cycle. During
a program cycle an attempted read of the last byte loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. During a
chip or sector erase operation, an attempt to read the
device will give a “0” on I/O7. Once the program or erase
cycle has completed, true data will be read from the device.
DATA polling may begin at any time during the program
cycle.
T O G G L E B I T : I n a d d i t i o n t o DATA p o l l i n g t h e
AT49BV004(T)/4096A(T) provides another method for
determining the end of a program or erase cycle. During a
program or erase operation, successive attempts to read
data from the device will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6
will stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
READY/BUSY: For the AT49BV004(T), pin 12 is an open
drain READY/BUSY output pin which provides another
method of detecting the end of a program or erase opera-
tion. RDY/BUSY is actively pulled low during the internal
program and erase cycles and it is released at the comple-
tion of the cycle. The open drain connection allows for OR-
tying of several devices to the same RDY/BUSY line.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the
AT49BV004(T)/4096A(T) in the following ways: (a) VCC
sense: if VCC is below 1.8V (typical), the program function
is inhibited. (b) VCC power on delay: once VCC has reached
the VCC sense level, the device will automatically time out
10 ms (typical) before programming. (c) Program inhibit:
holding any one of OE low, CE high or WE high inhibits
program cycles. (d) Noise filter: pulses of less than 15 ns
(typical) on the WE or CE inputs will not initiate a program
cycle.
INPUT LEVELS: While operating with a 2.7V to 3.6V
power supply, the address inputs and control inputs (OE,
CE, and WE) may be driven from 0 to 5.5V without
adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to VCC + 0.6V.
5
5 Page 
AT49BV004(T)/4096A(T)
Data Polling Characteristics(1)
Symbol Parameter
tDH
tOEH
tOE
tWR
Notes:
Data Hold Time
OE Hold Time
OE to Output Delay(2)
Write Recovery Time
1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
WE
CE
OE
tDH
I/O7
A0-A18
tOEH
tOE HIGH Z
An An
An
Toggle Bit Characteristics(1)
Symbol Parameter
tDH
tOEH
tOE
tOEHP
tWR
Notes:
Data Hold Time
OE Hold Time
OE to Output Delay(2)
OE High Pulse
Write Recovery Time
1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
Min Typ Max Units
10 ns
10 ns
ns
0 ns
tWR
An An
Min Typ Max Units
10 ns
10 ns
ns
150 ns
0 ns
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
11
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| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet AT49BV004T-12TI.PDF ] | |
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