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PDF AT49BV2048A Data sheet ( Hoja de datos )
| Número de pieza | AT49BV2048A | |
| Descripción | 2-megabit (256K x 8/128K x 16) Single 2.7-volt Battery-Voltage Flash Memory | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Single-voltage Read/Write Operation: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV)
• Fast Read Access Time – 70 ns
• Internal Erase/Program Control
• Sector Architecture
– One 8K Word (16K Bytes) Boot Block with Programming Lockout
– Two 4K Word (8K Bytes) Parameter Blocks
– One 112K Word (224K Bytes) Main Memory Array Block
• Fast Sector Erase Time – 10 Seconds
• Byte-by-byte or Word-by-word Programming – 30 µs Typical
• Hardware Data Protection
• Data Polling for End of Program Detection
• Low Power Dissipation
– 25 mA Active Current
– 50 µA CMOS Standby Current
• Typical 10,000 Write Cycles
Description
The AT49BV/LV2048A is a 3-volt, 2-megabit Flash memory organized as 262,144
words of 8 bits each or 128K words of 16 bits each. Manufactured with Atmel’s
advanced nonvolatile CMOS technology, the device offers access times to 70 ns with
power dissipation of just 67 mW at 2.7V read. When deselected, the CMOS standby
current is less than 50 µA.
The device contains a user-enabled “boot block” protection feature. The
AT49BV/LV2048A locates the boot block at lowest order addresses (“bottom boot”).
To allow for simple in-system reprogrammability, the AT49BV/LV2048A does not
require high input voltages for programming. Reading data out of the device is similar
to reading from an EPROM; it has standard CE, OE and WE inputs to avoid bus con-
tention. Reprogramming the AT49BV/LV2048A is performed by first erasing a block of
data and then programming on a byte-by-byte or word-by-word basis.
2-megabit
(256K x 8/
128K x 16)
Single 2.7-volt
Battery-Voltage™
Flash Memory
AT49BV2048A
AT49LV2048A
Pin Configurations
Pin Name
A0 - A16
CE
OE
WE
RESET
VPP
I/O0 - I/O15
I/O15(A-1)
BYTE
NC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
VPP can be left unconnected or connected to VCC, GND, 5V or
12V. The input has no effect on the operation of the device.
Data Inputs/Outputs
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
Selects Byte or Word Mode
No Connect
Rev. 1914D–FLASH–03/02
1
1 page  
AT49BV/LV2048A
PRODUCT IDENTIFICATION: The product identification mode identifies the device and man-
ufacturer as Atmel. It may be accessed by hardware or software operation. The hardware
operation mode can be used by an external programmer to identify the correct programming
algorithm for the Atmel product.
For details, see “Operating Modes” (for hardware operation) or “Software Product Identifica-
tion Entry/Exit” on page 13. The manufacturer and device codes are the same for both modes.
DATA POLLING: The AT49BV/LV2048A features Data Polling to indicate the end of a pro-
gram cycle. During a program cycle an attempted read of the last byte loaded will result in the
complement of the loaded data on I/O7. Once the program cycle has been completed, true
data is valid on all outputs and the next cycle may begin. During a chip or sector erase opera-
tion, an attempt to read the device will give a “0” on I/O7. Once the program or erase cycle has
completed, true data will be read from the device. Data Polling may begin at any time during
the program cycle.
TOGGLE BIT: In addition to Data Polling, the AT49BV/LV2048A provides another method for
determining the end of a program or erase cycle. During a program or erase operation, suc-
cessive attempts to read data from the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be
read. Examining the toggle bit may begin at any time during a program cycle.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs
to the AT49BV/LV2048A in the following ways: (a) VCC sense: if VCC is below 1.8V (typical),
the program function is inhibited. (b) VCC power on delay: once VCC has reached the VCC
sense level, the device will automatically time out 10 ms (typical) before programming. (c) Pro-
gram inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise
filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program
cycle.
INPUT LEVELS: While operating with a 2.7V to 3.6V power supply, the address and control
inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the opera-
tion of the device. The I/O lines can only be driven from 0 to VCC + 0.6V.
1914D–FLASH–03/02
5
5 Page 
AT49BV/LV2048A
Program Cycle Characteristics
Symbol
tBP
tAS
tAH
tDS
tDH
tWP
tWPH
tEC
Parameter
Byte/Word Programming Time
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Write Pulse Width
Write Pulse Width High
Erase Cycle Time
Program Cycle Waveforms
OE
Min Typ Max
30
0
70
70
0
70
50
10
PROGRAM CYCLE
CE
WE
A0-A16
tAS
DATA
t WP
tAH tDH
5555
2AAA
t DS
AA 55
t WPH
5555
ADDRESS
A0 INPUT DATA
t BP
5555
AA
Units
µs
ns
ns
ns
ns
ns
ns
seconds
Sector or Chip Erase Cycle Waveforms
(1)
OE
CE
WE
t AS
t WP
tAH t DH
t WPH
A0-A16
DATA
5555
2AAA
t DS
5555
5555
2AAA
Note 2
t EC
AA
WORD 0
55
WORD 1
80
WORD 2
AA
WORD 3
55
WORD 4
Note 3
WORD 5
Notes:
1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased.
(See note 4 under Command Definitions.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
1914D–FLASH–03/02
11
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| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet AT49BV2048A.PDF ] | |
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