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AT49LH002-33TC fiches techniques PDF

ATMEL Corporation - 2-megabit Firmware Hub and Low-Pin Count Flash Memory

Numéro de référence AT49LH002-33TC
Description 2-megabit Firmware Hub and Low-Pin Count Flash Memory
Fabricant ATMEL Corporation 
Logo ATMEL Corporation 





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AT49LH002-33TC fiche technique
Features
Complies with Intel® Low-Pin Count (LPC) Interface Specification Revision 1.1
– Supports both Firmware Hub (FWH) and LPC Memory Read and Write Cycles
Auto-detection of FWH and LPC Memory Cycles
– Can Be Used as FWH for Intel 8xx, E7xxx, and E8xxx Series Chipsets
– Can Be Used as LPC Flash for Non-Intel Chipsets
Flexible, Optimized Sectoring for BIOS Applications
– 16-Kbyte Top Boot Sector, Two 8-Kbyte Sectors, One 32-Kbyte Sector,
Three 64-Kbyte Sectors
– Or Memory Array Can Be Divided Into Four Uniform 64-Kbyte Sectors for Erasing
Two Configurable Interfaces
– FWH/LPC Interface for In-System Operation
– Address/Address Multiplexed (A/A Mux) Interface for Programming during
Manufacturing
FWH/LPC Interface
– Operates with the 33 MHz PCI Bus Clock
– 5-signal Communication Interface Supporting Byte Reads and Writes
– Two Hardware Write Protect Pins: TBL for Top Boot Sector and WP for All
Other Sectors
– Five General-purpose Input (GPI) Pins for System Design Flexibility
– Identification (ID) Pins for Multiple Device Selection
– Sector Locking Registers for Individual Sector Read and Write Protection
A/A Mux Interface
– 11-pin Multiplexed Address and 8-pin Data Interface
– Facilitates Fast In-System or Out-of-System Programming
Single Voltage Operation
– 3.0V to 3.6V Supply Voltage for Read and Write Operations
Industry-Standard Package Options
– 32-lead PLCC
– 40-lead TSOP
2-megabit
Firmware Hub
and Low-Pin
Count Flash
Memory
AT49LH002
Description
The AT49LH002 is a Flash memory device designed for use in PC and notebook BIOS
applications. The device complies with version 1.1 of Intel’s LPC Interface Specifica-
tion, providing support for both FWH and LPC memory read and write cycles. The
device can also automatically detect the memory cycle type to allow the AT49LH002
to be used as a FWH with Intel chipsets or as an LPC Flash with non-Intel chipsets.
Pin Configurations
PLCC
TSOP
[A7] GPI1
[A6] GPI0
[A5] WP
[A4] TBL
[A3] ID3
[A2] ID2
[A1] ID1
[A0] ID0
[I/O0] FWH0/LAD0
5
6
7
8
9
10
11
12
13
29 IC [IC]
28 GND
27 NC
26 NC
25 VCC
24 INIT [OE]
23 FWH4/LFRAME [WE]
22 RES [RDY/BSY]
21 RES [I/O7]
NC
[IC] IC
NC
NC
NC
NC
[A10] GPI4
NC
[R/C] CLK
VCC
NC
[RST] RST
NC
NC
[A9] GPI3
[A8] GPI2
[A7] GPI1
[A6] GPI0
[A5] WP
[A4] TBL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 GND
39 VCC
38 FWH4/LFRAME [WE]
37 INIT [OE]
36 RES [RDY/BSY]
35 RES [I/O7]
34 RES [I/O6]
33 RES [I/O5]
32 RES [I/O4]
31 VCC
30 GND
29 GND
28 FWH3/LAD3 [I/O3]
27 FWH2/LAD2 [I/O2]
26 FWH1/LAD1 [I/O1]
25 FWH0/LAD0 [I/O0]
24 ID0 [A0]
23 ID1 [A1]
22 ID2 [A2]
21 ID3 [A3]
Note: [ ] Designates A/A Mux Interface.
3377B–FLASH–9/03
1

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