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PDF ADV7127 Data sheet ( Hoja de datos )
| Número de pieza | ADV7127 | |
| Descripción | CMOS/ 240 MHz 10-Bit High Speed Video DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
CMOS, 240 MHz
10-Bit High Speed Video DAC
ADV7127
FEATURES
240 MSPS Throughput Rate
10-Bit D/A Converters
SFDR
–70 dB typ: fCLK = 50 MHz; fOUT = 1 MHz
–53 dB typ: fCLK = 140 MHz; fOUT = 40 MHz
RS-343A/RS-170 Compatible Output
Complementary Outputs
DAC Output Current Range: 2 mA to 26 mA
TTL Compatible Inputs
Internal Voltage Reference (1.23 V) on TSSOP Package
Single Supply +5 V/+3.3 V Operation
28-Lead SOIC Package and 24-Lead TSSOP Package
Low Power Dissipation (30 mW min @ 3 V)
Low Power Standby Mode (10 mW min @ 3 V)
Power-Down Mode (60 mW min @ 3 V)
Power-Down Mode Available on TSSOP Package
Industrial Temperature Range (–40؇C to +85؇C)
APPLICATIONS
Digital Video Systems (1600 ؋ 1200 @ 100 Hz)
High Resolution Color Graphics
Digital Radio Modulation
Image Processing
Instrumentation
Video Signal Reconstruction
Direct Digital Synthesis (DDS)
Wireless LAN
FUNCTIONAL BLOCK DIAGRAM
VAA
D9–D0
10
DATA
REGISTER
10
DAC
PDOWN*
PSAVE
CLOCK
POWER–
DOWN
MODE
GND
RSET
*ON TSSOP VERSION ONLY
VOLTAGE*
REFERENCE
CIRCUIT
ADV7127
COMP
IOUT
IOUT
VREF
GENERAL DESCRIPTION
The ADV7127 (ADV®) is a high speed, digital-to-analog con-
vertor on a single monolithic chip. It consists of a 10-bit,
video D/A converter with on-board voltage reference, comple-
mentary outputs, a standard TTL input interface and high
impedance analog output current sources.
The ADV7127 has a 10-bit wide input port. A single +5 V/
+3.3 V power supply and clock are all that are required to make
the part functional.
The ADV7127 is fabricated in a CMOS process. Its monolithic
CMOS construction ensures greater functionality with lower
power dissipation. The ADV7127 is available in a small outline
28-lead SOIC or 24-lead TSSOP package.
The ADV7127 TSSOP package also has a power-down mode.
Both ADV7127 packages have a power standby mode.
The ADV7127 TSSOP package has an on-board voltage refer-
ence circuit. The ADV7127 SOIC package requires an external
reference.
PRODUCT HIGHLIGHTS
1. 240 MSPS Throughput.
2. Guaranteed monotonic to 10 bits.
3. Compatible with a wide variety of high resolution color
graphics systems including RS-343A and RS-170A.
ADV is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
1 page  
ADV7127
3.3 V TSSOP SPECIFICATIONS1 (VAA = +3.0 V–3.6 V, VREF = 1.235 V, RSET = 560 ⍀, CL = 10 pF. All specifications TMINto TMAX2
unless otherwise noted, TJ MAX = 110؇C)
Parameter
Min Typ Max
Units
Test Conditions
STATIC PERFORMANCE
Resolution (Each DAC)
Integral Nonlinearity (BSL)
Differential Nonlinearity
10
–1 0.5 +1
–1 0.25 +1
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
PDOWN Input High Voltage3
2.0
0.8
2.1
PDOWN Input Low Voltage3
0.6
Input Current, IIN
–1 +1
PSAVE Pull-Up Current
20
Input Capacitance, CIN
10
Bits
LSB
LSB
RSET = 680 Ω
RSET = 680 Ω
RSET = 680 Ω
V
V
V
V
µA VIN = 0.0 V or VDD
µA
pF
ANALOG OUTPUTS
Output Current
Output Compliance Range, VOC
Output Impedance, ROUT
Output Capacitance, COUT
Offset Error
Gain Error4
2.0 18.5
0 +1.4
70
10
00
0
mA
V
kΩ
pF
% FSR
% FSR
Tested with DAC Output = 0 V
FSR = 17.62 mA
VOLTAGE REFERENCE (Ext.)
Reference Range, VREF
VOLTAGE REFERENCE (Int.)5
Reference Range, VREF
1.12 1.235 1.35
1.235
V
V
POWER DISSIPATION
Digital Supply Current6
Digital Supply Current6
Digital Supply Current6
Analog Supply Current
Analog Supply Current
Standby Supply Current
PDOWN Supply Current
Power Supply Rejection Ratio
12
2.5 4.5
46
22 25
5
2.6 3
20
0.1 0.5
mA
mA
mA
mA
mA
mA
µA
%/%
fCLK = 50 MHz
fCLK = 140 MHz
fCLK = 240 MHz
RSET = 560 Ω
RSET = 4933 Ω
PSAVE = Low, Digital and Control
Inputs at VDD
NOTES
1These max/min specifications are guaranteed by characterization to be over 3.0 V to 3.6 V range.
2Temperature range TMIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz.
3This power-down feature is only available on the ADV7127 in the TSSOP package.
4Gain error = ((Measured (FSC)/Ideal (FSC) –1) × 100), where Ideal = VREF /RSET × K × (3FFH) and K = 7.9896.
5Internal voltage reference is available only on the ADV7127 TSSOP package.
6Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V DD.
Specifications subject to change without notice.
REV. 0
–5–
5 Page 
ADV7127
3 V–Typical Performance Characteristics
(VAA = +3 V, VREF = 1.235 V, IOUT =17.62 A, 50 ⍀ Doubly Terminated Load, Differential Output Loading, TA = +25؇C)
70
60
SFDR (DE)
50
SFDR (SE)
40
30
20
10
0
0.1 2.51 5.04 20.2 40.4 100
FREQUENCY – MHz
Figure 11. SFDR vs. fOUT @ fCLOCK =
140 MHz (Single-Ended and
Differential)
80
SFDR (DE)
70
SFDR (SE)
60
50
40
30
20
10
0
0.1
1.0 2.51 5.04 20.2 40.4 100
FREQUENCY – MHz
Figure 12. SFDR vs. fOUT @ fCLOCK =
50 MHz (Single-Ended and
Differential)
72.0
71.8
71.6
SFDR (fOUT = 1MHz)
71.4
71.2
71.0
70.8
70.6
70.4
0
20 85 145
TEMPERATURE – ؇C
165
Figure 13. SFDR vs. Temperature @
fCLOCK = 50 MHz, (fOUT = 1 MHz)
76
2nd HARMONIC
74
72 4th HARMONIC
70
3rd HARMONIC
68
66
64
62
60
58
56
0 50 100 140 160
FREQUENCY – MHz
Figure 14. THD vs. fCLOCK @ fOUT =
2 MHz (2nd, 3rd and 4th Harmonics)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
2 17.62
IOUT – mA
20
Figure 15. Linearity vs. IOUT
1.00
0.50
0.75
0.00
–0.50
1023
–0.42
–1.00
CODE– INL
Figure 16. Typical Linearity
–5.0
2
VAA = 3.3V
–45.0
CLK = 140MHz
fOUT = 2.5MHz
SING O/P
1
–85.0
0kHz
START
35.0MHz
70.0MHz
STOP
Figure 17. Single-Tone SFDR @
fCLOCK = 140 MHz (fOUT1 = 2 MHz)
–5.0
2
VAA = 3.3V
CLK = 140MHz
fOUT = 20MHz
SING O/P
–5.0
2 VAA = 3.3V
CLK = 140MHz
DUAL TONE
SING O/P
–45.0
1
–85.0
0kHz
START
35.0MHz
70.0MHz
STOP
Figure 18. Single-Tone SFDR @
fCLOCK = 140 MHz (fOUT1 = 20 MHz)
–45.0
1
–85.0 0kHz
START
35.0MHz
70.0MHz
STOP
Figure 19. Dual-Tone SFDR @ fCLOCK
= 140 MHz (fOUT1 = 13.5 MHz, fOUT2 =
14.5 MHz)
REV. 0
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADV7127.PDF ] | |
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