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PDF AD807 Data sheet ( Hoja de datos )
| Número de pieza | AD807 | |
| Descripción | Fiber Optic Receiver | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a Fiber Optic Receiver with Quantizer and
Clock Recovery and Data Retiming
AD807
FEATURES
Meets CCITT G.958 Requirements
for STM-1 Regenerator—Type A
Meets Bellcore TR-NWT-000253 Requirements for OC-3
Output Jitter: 2.0 Degrees RMS
155 Mbps Clock Recovery and Data Retiming
Accepts NRZ Data, No Preamble Required
Phase-Locked Loop Type Clock Recovery—
No Crystal Required
Quantizer Sensitivity: 2 mV
Level Detect Range: 2.0 mV to 30 mV
Single Supply Operation: +5 V or –5.2 V
Low Power: 170 mW
10 KH ECL/PECL Compatible Output
Package: 16-Lead Narrow 150 mil SOIC
PRODUCT DESCRIPTION
The AD807 provides the receiver functions of data quantization,
signal level detect, clock recovery and data retiming for 155 Mbps
NRZ data. The device, together with a PIN diode/preamplifier
combination, can be used for a highly integrated, low cost, low
power SONET OC-3 or SDH STM-1 fiber optic receiver.
The receiver front end signal level detect circuit indicates when
the input signal level has fallen below a user adjustable thresh-
old. The threshold is set with a single external resistor. The
signal level detect circuit 3 dB optical hysteresis prevents chatter
at the signal level detect output.
The PLL has a factory-trimmed VCO center frequency and a
frequency acquisition control loop that combine to guarantee
frequency acquisition without false lock. This eliminates a
reliance on external components such as a crystal or a SAW
filter, to aid frequency acquisition.
The AD807 acquires frequency and phase lock on input data
using two control loops that work without requiring external
control. The frequency acquisition control loop initially acquires
the frequency of the input data, acquiring frequency lock on
random or scrambled data without the need for a preamble. At
frequency lock, the frequency error is zero and the frequency
detector has no further effect. The phase acquisition control
loop then works to ensure that the output phase tracks the input
phase. A patented phase detector has virtually eliminated pattern
jitter throughout the AD807.
The device VCO uses a ring oscillator architecture and patented
low noise design techniques. Jitter is 2.0 degrees rms. This low
jitter results from using a fully differential signal architecture,
Power Supply Rejection Ratio circuitry and a dielectrically
isolated process that provides immunity from extraneous signals
on the IC. The device can withstand hundreds of millivolts of
power supply noise without an effect on jitter performance.
The user sets the jitter peaking and acquisition time of the PLL
by choosing a damping factor capacitor whose value determines
loop damping. CCITT G.958 Type A jitter transfer require-
ments can easily be met with a damping factor of 5 or greater.
Device design guarantees that the clock output frequency will
drift by less than 20% in the absence of input data transitions.
Shorting the damping factor capacitor, CD, brings the clock
output frequency to the VCO center frequency.
The AD807 consumes 170 mW and operates from a single
power supply at either +5 V or –5.2 V.
FUNCTIONAL BLOCK DIAGRAM
QUANTIZER
PIN +
NIN –
THRADJ
SIGNAL
LEVEL
DETECTOR
LEVEL
DETECT
COMPARATOR/
BUFFER
+
–
⌽DET
COMPENSATING
ZERO
PHASE-LOCKED LOOP
FDET
AD807
RETIMING
DEVICE
SDOUT
CF1 CF2
⌺
LOOP
FILTER
VCO
CLKOUTP
CLKOUTN
DATAOUTP
DATAOUTN
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
AD807
DEFINITION OF TERMS
Maximum, Minimum and Typical Specifications
Specifications for every parameter are derived from statistical
analyses of data taken on multiple devices from multiple wafer
lots. Typical specifications are the mean of the distribution of
the data for that parameter. If a parameter has a maximum (or a
minimum), that value is calculated by adding to (or subtracting
from) the mean six times the standard deviation of the distribution.
This procedure is intended to tolerate production variations: if the
mean shifts by 1.5 standard deviations, the remaining 4.5 standard
deviations still provide a failure rate of only 3.4 parts per million.
For all tested parameters, the test limits are guardbanded to
account for tester variation to thus guarantee that no device is
shipped outside of data sheet specifications.
Input Sensitivity and Input Overdrive
Sensitivity and Overdrive specifications for the Quantizer involve
offset voltage, gain and noise. The relationship between the logic
output of the quantizer and the analog voltage input is shown in
Figure 1.
For sufficiently large positive input voltage the output is always
Logic 1 and similarly, for negative inputs, the output is always
Logic 0. However, the transitions between output Logic Levels 1
and 0 are not at precisely defined input voltage levels, but occur
over a range of input voltages. Within this Zone of Confusion,
the output may be either 1 or 0, or it may even fail to attain
a valid logic state. The width of this zone is determined by the
input voltage noise of the quantizer (650 µV at the 1 × 10–10
confidence level). The center of the Zone of Confusion is the
quantizer input offset voltage (± 500 µV maximum). Input Over-
drive is the magnitude of signal required to guarantee correct
logic level with 1 × 10–10 confidence level.
With a single-ended PIN-TIA (Figure 3), ac coupling is used and
the inputs to the Quantizer are dc biased at some common-mode
potential. Observing the Quantizer input with an oscilloscope
probe at the point indicated shows a binary signal with average
value equal to the common-mode potential and instantaneous
values both above and below the average value. It is convenient
to measure the peak-to-peak amplitude of this signal and call the
minimum required value the Quantizer Sensitivity. Referring to
Figure 1, since both positive and negative offsets need to be
accommodated, the Sensitivity is twice the Overdrive. The AD807
Quantizer has 2 mV Sensitivity.
With a differential TIA (Figure 3), Sensitivity seems to improve
from observing the Quantizer input with an oscilloscope probe.
This is an illusion caused by the use of a single-ended probe. A
1 mV peak-to-peak signal appears to drive the AD807 Quantizer.
However, the single-ended probe measures only half the signal.
The true Quantizer input signal is twice this value since the
other Quantizer input is a complementary signal to the sig-
nal being observed.
Response Time
Response time is the delay between removal of the input signal
and indication of Loss of Signal (LOS) at SDOUT. The response
time of the AD807 (1.5 µs maximum) is much faster than the
SONET/SDH requirement (3 µs ≤ response time ≤ 100 µs). In
practice, the time constant of the ac coupling at the Quantizer
input determines the LOS response time.
Nominal Center Frequency
This is the frequency at which the VCO will oscillate with the
loop damping capacitor, CD, shorted.
Tracking Range
This is the range of input data rates over which the AD807 will
remain in lock.
Capture Range
This is the range of input data rates over which the AD807 will
acquire lock.
Static Phase Error
This is the steady-state phase difference, in degrees, between the
recovered clock sampling edge and the optimum sampling instant,
which is assumed to be halfway between the rising and falling
edges of a data bit. Gate delays between the signals that define
static phase error, and IC input and output signals prohibit
direct measurement of static phase error.
Data Transition Density, ρ
This is a measure of the number of data transitions, from “0” to
“1” and from “1” to “0,” over many clock periods. ρ is the ratio
(0 ≤ ρ ≤ 1) of data transitions to bit periods.
Jitter
This is the dynamic displacement of digital signal edges from
their long term average positions, measured in degrees rms or
Unit Intervals (UI). Jitter on the input data can cause dynamic
phase errors on the recovered clock sampling edge. Jitter on the
recovered clock causes jitter on the retimed data.
Output Jitter
This is the jitter on the retimed data, in degrees rms, due to a
specific pattern or some pseudorandom input data sequence
(PRN Sequence).
Jitter Tolerance
Jitter Tolerance is a measure of the AD807’s ability to track a
jittery input data signal. Jitter on the input data is best thought
of as phase modulation, and is usually specified in unit intervals.
The PLL must provide a clock signal that tracks the phase
modulation in order to accurately retime jittered data. In order
for the VCO output to have a phase modulation that tracks the
input jitter, some modulation signal must be generated at the
output of the phase detector. The modulation output from the
phase detector can only be produced by a phase error between
its data input and its clock input. Hence, the PLL can never
perfectly track jittered data. However, the magnitude of the
phase error depends on the gain around the loop. At low fre-
quencies, the integrator of the AD807 PLL provides very high
gain, and thus very large jitter can be tracked with small phase
errors between input data and recovered clock. At frequencies
closer to the loop bandwidth, the gain of the integrator is much
smaller, and thus less input jitter can be tolerated. The AD807
output will have a bit error rate less than 1 × 10–10 when in lock
and retiming input data that has the CCITT G.958 specified
jitter applied to it.
Jitter Transfer (Refer to Figure 11)
The AD807 exhibits a low-pass filter response to jitter applied to
its input data.
–4– REV. B
5 Page 
AD807
C1 0.1F
J1
DATAOUTN
DATAOUTP
J2
J3
CLKOUTN
CLKOUTP
J4
R1
100⍀
C2 0.1F
R2
100⍀
C3 0.1F
C4 0.1F
C5 0.1F
R3 R4
100⍀ 100⍀
C2
0.1F
SDOUT
TP7
R9
R5 100⍀ 154⍀
R6 100⍀
R10
154⍀
1 DATAOUTN
2 DATAOUTP
VEE 16
SDOUT 15
R7 100⍀
R8 100⍀
C7
3 VCC2
4 CLKOUTN
5 CLKOUTP
AVCC2 14
PIN 13
NIN 12
R11
154⍀
6 VCC1
AVCC1 11
C8 TP1
7 CF1
THRADJ 10
CD
R12
154⍀
8 CF2
AVEE 9
TP2 AD807
R17 C12
3.65k⍀ 2.2F
R16
301⍀
C11
R14 R15
50⍀ 50⍀
C10
TP6
R13
THRADJ
TP5
C15
0.1F
C14
0.1F
C13
0.1F
NOTES:
1. ALL CAPACITORS ARE CHIP,
15pF ARE MICA.
2. 150nH ARE SMT
3. C7, C8, C10, C11 ARE 0.1F
BYPASS CAPACITORS
C9
10F
TP4
TP3
5V
ABB HAFO 1A227
FC HOUSING
0.8A/W, 0.7pF
2.5GHz
1 NC
2 IIN
3 NC
+VS 8
+OUT 7
–OUT 6
0.1F 0.01F
4 VBYP
–VS 5
AD8015
NC = NO CONNECT
0.1F
10F
50⍀
LINE
150nH
15pF
150nH
15pF
Figure 14. Low Cost 155 Mbps Fiber Optic Receiver Schematic
50⍀
LINE
Table I. AD807—AD8015 Fiber Optic Receiver Circuit:
Output Bit Error Rate and Output Jitter vs. Input Power
Average Optical
Input Power
(dBm)
–6.4
–6.5
–6.6
–6.7
–7.0 to –35.5
–36.0
–36.5
–37.0
–38.0
–39.0
–39.2
–39.3
Output Bit
Error Rate
Loses Lock
7.5 × 10–3
9.4 × 10–4
0 × 10–14
0 × 10–14
3 × 10–12
4.8 × 10–10
2.8 × 10–8
1.3 × 10–5
1.0 × 10–3
1.9 × 10–3
Loses Lock
Output Jitter
(ps rms)
<40
<40
503mV
100mV/
DIV
–497mV
48.12ns
1ns/DIV
58.12ns
Figure 15. Receiver Output (Data) Eye Diagram,
–7.0 dBm Optical Input
503mV
APPLICATIONS
Low Cost 155 Mbps Fiber Optic Receiver
The AD807 and AD8015 can be used together for a complete
155 Mbps Fiber Optic Receiver (Quantizer and Clock Recovery,
and Transimpedance Amplifier) as shown in Figure 14.
The PIN diode front end is connected to a single mode 1300 nm
laser source. The PIN diode has 3.3 V reverse bias, 0.8 A/W
responsively, 0.7 pF capacitance, and 2.5 GHz bandwidth.
The AD8015 outputs (POUT and NOUT) drive a differential,
constant impedance (50 Ω) low-pass filter with a 3 dB cutoff
of 100 MHz. The outputs of the low-pass filter are ac coupled
to the AD807 inputs (PIN and NIN). The AD807 PLL damp-
ing factor is set at 7 using a 0.22 µF capacitor.
100mV/
DIV
–497mV
49.12ns
1ns/DIV
59.12ns
Figure 16. Receiver Output (Data) Eye Diagram,
–36.0 dBm Optical Input
–10–
REV. B
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet AD807.PDF ] | |
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