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PDF AD9203 Data sheet ( Hoja de datos )
| Número de pieza | AD9203 | |
| Descripción | A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
CMOS 10-Bit, 40 MSPS sampling A/D converter
Power dissipation: 74 mW (3 V supply, 40 MSPS)
17 mW (3 V supply, 5 MSPS)
Operation between 2.7 V and 3.6 V supply
Differential nonlinearity: −0.25 LSB
Power-down (standby) mode, 0.65 mW
ENOB: 9.55 @ fIN = 20 MHz
Out-of-range indicator
Adjustable on-chip voltage reference
IF undersampling up to fIN = 130 MHz
Input range: 1 V to 2 V p-p differential or single-ended
Adjustable power consumption
Internal clamp circuit
APPLICATIONS
CCD imaging
Video
Portable instrumentation
IF and baseband communications
Cable modems
Medical ultrasound
GENERAL DESCRIPTION
The AD9203 is a monolithic low power, single supply, 10-bit,
40 MSPS analog-to-digital converter, with an on-chip voltage
reference. The AD9203 uses a multistage differential pipeline
architecture and guarantees no missing codes over the full
operating temperature range. Its input range may be adjusted
between 1 V and 2 V p-p.
The AD9203 has an onboard programmable reference. An
external reference can also be chosen to suit the dc accuracy
and temperature drift requirements of an application.
An external resistor can be used to reduce power consumption
when operating at lower sampling rates. This yields power
savings for users who do not require the maximum sample rate.
This feature is especially useful at sample rates far below 40
MSPS. Excellent performance is still achieved at reduced power.
For example, 9.7 ENOB performance may be realized with only
17 mW of power, using a 5 MHz clock.
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary or
twos complementary output format by using the DFS pin. An
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
10-Bit, 40 MSPS, 3 V, 74 mW
A/D Converter
AD9203
CLAMP
CLAMPIN
AINP
AINN
REFTF
REFBF
VREF
REFSENSE
FUNCTIONAL BLOCK DIAGRAM
CLK AVDD
DRVDD
AD9203
SHA
A/D D/A
GAIN
SHA
A/D D/A
GAIN
A/D
CORRECTION LOGIC
BANDGAP
REFERENCE
OUTPUT BUFFERS
+
–
0.5V
10
AVSS
PWRCON
DFS
DRVSS
Figure 1.
STBY
3-STATE
OTR
D9 (MSB)
D0 (LSB)
out-of-range signal (OTR) indicates an overflow condition that
can be used with the most significant bit to determine over- or
underrange.
The AD9203 can operate with a supply range from 2.7 V to 3.6
V, an attractive option for low power operation in high-speed
portable applications.
The AD9203 is specified over industrial (−40°C to +85°C)
temperature ranges and is available in a 28-lead TSSOP package.
PRODUCT HIGHLIGHTS
Low Power—The AD9203 consumes 74 mW on a 3 V supply
operating at 40 MSPS. In standby mode, power is reduced to
0.65 mW.
High Performance—Maintains better than 9.55 ENOB at 40
MSPS input signal from dc to Nyquist.
Very Small Package—The AD9203 is available in a 28-lead
TSSOP.
Programmable Power—The AD9203 power can be further
reduced by using an external resistor at lower sample rates.
Built-In Clamp Function—Allows dc restoration of video
signals.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
With
Respect to Min
Max
AVDD
AVSS
–0.3 +3.9
DRVDD
DRVSS
–0.3 +3.9
AVSS
DRVSS
–0.3 +0.3
AVDD
DRVDD
–3.9 +3.9
REFCOM
AVSS
–0.3 +0.3
CLK
AVSS
–0.3 AVDD + 0.3
Digital Outputs DRVSS
–0.3 DRVDD + 0.3
AINP
AINN
AVSS AVDD + 0.3
–0.3
VREF
AVSS
–0.3 AVDD + 0.3
REFSENSE
AVSS
–0.3 AVDD + 0.3
REFTF, REFBF
AVSS
–0.3 AVDD + 0.3
STBY
AVSS
–0.3 AVDD + 0.3
CLAMP
AVSS
–0.3 AVDD + 0.3
CLAMPIN
AVSS
–0.3 AVDD + 0.3
PWRCON
AVSS
–0.3 AVDD + 0.3
DFS
AVSS
–0.3 AVDD + 0.3
3-STATE
AVSS
–0.3 AVDD + 0.3
Junction
Temperature
Storage
Temperature
150
–65 +150
Lead
Temperature
(10 s)
300
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
AD9203
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
28-Lead TSSOP
JA = 97.9°C/W
JC = 14.0°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 5 of 28
5 Page 
AD9203
OPERATIONS
THEORY OF OPERATION
OPERATIONAL MODES
The AD9203 implements a pipelined multistage architecture to
achieve high sample rates while consuming low power. It
distributes the conversion over several smaller A/D subblocks,
refining the conversion with progressively higher accuracy as it
passes the results from stage to stage. As a consequence of the
distributed conversion, the AD9203 requires a small fraction of
the 1023 comparators used in a traditional 10-bit flash-type
A/D. A sample-and-hold function within each of the stages
permits the first stage to operate on a new input sample while
the remaining stages operate on preceding samples.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash A/D connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each one of the stages to facilitate digital
correction of flash errors. The last stage simply consists of a
flash A/D.
The input of the AD9203 incorporates a novel structure that
merges the input sample-and-hold amplifier (SHA) and the first
pipeline residue amplifier into a single, compact switched
capacitor circuit. This structure achieves considerable noise and
power savings over a conventional implementation that uses
separate amplifiers by eliminating one amplifier in the pipeline.
By matching the sampling network of the input SHA with the
first stage flash A/D, the AD9203 can sample inputs well
beyond the Nyquist frequency with no degradation in
performance. Sampling occurs on the falling edge of the clock.
The AD9203 may be connected in several input configurations,
as shown in Table 4.
The AD9203 may be driven differentially from a source that
keeps the signal peaks within the power supply rails.
Alternatively, the input may be driven into AINP or AINN from
a single-ended source. The input span will be 2 the
programmed reference voltage. One input will accept the signal,
while the opposite input will be set to midscale by connecting it
to the internal or an external reference. For example, a 2 V p-p
signal may be applied to AINP while a 1 V reference is applied
to AINN. The AD9203 will then accept a signal varying
between 2 V and 0 V. See Figure 19, Figure 20, and Figure 21 for
more details.
The single-ended (ac-coupled) input of the AD9203 may also be
clamped to ground by the internal clamp switch. This is
accomplished by connecting the CLAMP pin to AINN or AINP.
Digital output formats may be configured in binary and twos
complement. This is determined by the potential on the DFS
pin. If the pin is set to Logic 0, the data will be in straight binary
format. If the pin is asserted to Logic 1, the data will be in twos
complement format.
Power consumption may be reduced by placing a resistor
between PWRCON and AVSS. This may be done to conserve
power when not encoding high-speed analog input frequencies
or sampling at the maximum conversion rate. See the
Power Control section for more information.
Table 4. Modes
Name
1 V Differential
2 V Differential
1 V Single-Ended
2 V Single-Ended
Figure Number
Figure 28 with VREF Connected to
REFSENSE
Figure 28 with REFSENSE Connected to
AGND
Figure 20
Figure 19
Advantages
Differential Modes Yield the Best Dynamic Performance
Differential Modes Yield the Best Dynamic Performance
Video and Applications Requiring Clamping Require Single-Ended Inputs
Video and Applications Requiring Clamping Require Single-Ended Inputs
Rev. B | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD9203.PDF ] | |
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