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PDF AD9243 Data sheet ( Hoja de datos )
| Número de pieza | AD9243 | |
| Descripción | Monolithic A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Monolithic 14-Bit, 3 MSPS A/D Converter
Low Power Dissipation: 110 mW
Single +5 V Supply
Integral Nonlinearity Error: 2.5 LSB
Differential Nonlinearity Error: 0.6 LSB
Input Referred Noise: 0.36 LSB
Complete: On-Chip Sample-and-Hold Amplifier and
Voltage Reference
Signal-to-Noise and Distortion Ratio: 79.0 dB
Spurious-Free Dynamic Range: 91.0 dB
Out-of-Range Indicator
Straight Binary Output Data
44-Lead MQFP
Complete 14-Bit, 3.0 MSPS
Monolithic A/D Converter
AD9243
FUNCTIONAL BLOCK DIAGRAM
CLK
AVDD
DVDD DRVDD
VINA
VINB
CML
CAPT
CAPB
VREF
SENSE
SHA
MDAC1
GAIN = 16
5
A/D
5
MDAC2
GAIN = 8
MDAC3
GAIN = 8
4
A/D
4
A/D
44
DIGITAL CORRECTION LOGIC
14
OUTPUT BUFFERS
A/D
4
MODE
SELECT
1V
AD9243
REFCOM
AVSS
DVSS DRVSS
OTR
BIT 1
(MSB)
BIT 14
(LSB)
PRODUCT DESCRIPTION
The AD9243 is a 3 MSPS, single supply, 14-bit analog-to-
digital converter (ADC). It combines a low cost, high speed
CMOS process and a novel architecture to achieve the resolution
and speed of existing hybrid implementations at a fraction of the
power consumption and cost. It is a complete, monolithic ADC
with an on-chip, high performance, low noise sample-and-hold
amplifier and programmable voltage reference. An external refer-
ence can also be chosen to suit the dc accuracy and temperature
drift requirements of the application. The device uses a multistage
differential pipelined architecture with digital output error correc-
tion logic to guarantee no missing codes over the full operating
temperature range.
The input of the AD9243 is highly flexible, allowing for easy
interfacing to imaging, communications, medical, and data-
acquisition systems. A truly differential input structure allows
for both single-ended and differential input interfaces of varying
input spans. The sample-and-hold amplifier (SHA) is equally
suited for both multiplexed systems that switch full-scale voltage
levels in successive channels as well as sampling single-channel
inputs at frequencies up to and beyond the Nyquist rate. Also,
the AD9243 performs well in communication systems employ-
ing Direct-IF Down Conversion since the SHA in the differen-
tial input mode can achieve excellent dynamic performance well
beyond its specified Nyquist frequency of 1.5 MHz.
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range (OTR) signal indicates an
overflow condition which can be used with the most significant
bit to determine low or high overflow.
PRODUCT HIGHLIGHTS
The AD9243 offers a complete single-chip sampling 14-bit,
analog-to-digital conversion function in a 44-lead Metric Quad
Flatpack.
Low Power and Single Supply
The AD9243 consumes only 110 mW on a single +5 V power
supply.
Excellent DC Performance Over Temperature
The AD9243 provides no missing codes, and excellent tempera-
ture drift performance over the full operating temperature range.
Excellent AC Performance and Low Noise
The AD9243 provides nearly 13 ENOB performance and has an
input referred noise of 0.36 LSB rms.
Flexible Analog Input Range
The versatile onboard sample-and-hold (SHA) can be configured
for either single ended or differential inputs of varying input spans.
Flexible Digital Outputs
The digital outputs can be configured to interface with +3 V and
+5 V CMOS logic families.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
1 page  
AD9243
SWITCHING SPECIFICATIONS (TMIN to TMAX with AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, CL = 20 pF)
Parameters
Clock Period1
CLOCK Pulsewidth High
CLOCK Pulsewidth Low
Output Delay
Pipeline Delay (Latency)
Symbol
tC
tCH
tCL
tOD
AD9243
333
150
150
8
13
19
3
Units
ns min
ns min
ns min
ns min
ns typ
ns max
Clock Cycles
NOTES
1The clock period may be extended to 1 ms without degradation in specified performance @ +25 °C.
Specifications subject to change without notice.
ANALOG
INPUT
INPUT
CLOCK
DATA
OUTPUT
S1 S2
tC
tCH tCL
S3
S4
Figure 1. Timing Diagram
tOD
DATA 1
ABSOLUTE MAXIMUM RATINGS*
Parameter
With
Respect
to Min
Max
Units
THERMAL CHARACTERISTICS
Thermal Resistance
44-Lead MQFP
θJA = 53.2°C/W
θJC = 19°C/W
ORDERING GUIDE
Model
Temperature
Range
AD9243AS –40°C to +85°C
AD9243EB Evaluation Board
*S = Metric Quad Flatpack.
Package
Description
44-Lead MQFP
Package
Option*
S-44
AVDD
AVSS –0.3 +6.5
V
DVDD
DVSS –0.3 +6.5
V
AVSS
DVSS –0.3 +0.3
V
AVDD
DVDD –6.5 +6.5
V
DRVDD
DRVSS –0.3 +6.5
V
DRVSS
AVSS –0.3 +0.3
V
REFCOM
AVSS –0.3 +0.3
V
CLK
DVSS –0.3 DVDD + 0.3 V
Digital Outputs
DRVSS –0.3 DRVDD + 0.3 V
VINA, VINB
AVSS –0.3 AVDD + 0.3 V
VREF
AVSS –0.3 AVDD + 0.3 V
SENSE
AVSS –0.3 AVDD + 0.3 V
CAPB, CAPT
AVSS –0.3 AVDD + 0.3 V
Junction Temperature
+150
°C
Storage Temperature
–65 +150
°C
Lead Temperature
(10 sec)
+300
°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
PIN CONNECTIONS
44 43 42 41 40 39 38 37 36 35 34
DVSS 1
AVSS 2
DVDD 3
AVDD 4
DRVSS 5
DRVDD 6
CLK 7
NC 8
NC 9
NC 10
(LSB) BIT 14 11
PIN 1
IDENTIFIER
AD9243
TOP VIEW
(Not to Scale)
33 REFCOM
32 VREF
31 SENSE
30 NC
29 AVSS
28 AVDD
27 NC
26 NC
25 OTR
24 BIT 1 (MSB)
23 BIT 2
12 13 14 15 16 17 18 19 20 21 22
NC = NO CONNECT
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9243 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. A
5 Page 
AD9243
VCC
RS* AD9243
VINA
RS*
VINB
VEE VREF
10F
0.1F
SENSE
REFCOM
*OPTIONAL SERIES RESISTOR
Figure 25. Series Resistor Isolates Switched-Capacitor
SHA Input from Op Amp. Matching Resistors Improve
SNR Performance
The optimum size of this resistor is dependent on several factors
which include the AD9243 sampling rate, the selected op amp,
and the particular application. In most applications, a 30 Ω to
50 Ω resistor is sufficient. However, some applications may re-
quire a larger resistor value to reduce the noise bandwidth or
possibly limit the fault current in an overvoltage condition.
Other applications may require a larger resistor value as part of
an anti-aliasing filter. In any case, since the THD performance
is dependent on the series resistance and the above mentioned
factors, optimizing this resistor value for a given application is
encouraged.
A slight improvement in SNR performance and dc offset perfor-
mance is achieved by matching the input resistance connected
to VINA and VINB. The degree of improvement is dependent on
the resistor value and the sampling rate. For series resistor
values greater than 100 Ω, the use of a matching resistor is
encouraged.
The noise or small-signal bandwidth of the AD9243 is the same
as its full-power bandwidth. For noise sensitive applications, the
excessive bandwidth may be detrimental and the addition of a
series resistor and/or shunt capacitor can help limit the wide-
band noise at the A/D’s input by forming a low-pass filter.
Note, however, that the combination of this series resistance
with the equivalent input capacitance of the AD9243 should be
evaluated for those time-domain applications that are sensitive
to the input signal’s absolute settling time. In applications where
harmonic distortion is not a primary concern, the series resis-
tance may be selected in combination with the SHA’s nominal
16 pF of input capacitance to set the filter’s 3 dB cutoff frequency.
A better method of reducing the noise bandwidth, while possi-
bly establishing a real pole for an antialiasing filter, is to add
some additional shunt capacitance between the input (i.e.,
VINA and/or VINB) and analog ground. Since this additional
shunt capacitance combines with the equivalent input capaci-
tance of the AD9243, a lower series resistance can be selected to
establish the filter’s cutoff frequency while not degrading the
distortion performance of the device. The shunt capacitance
also acts like a charge reservoir, sinking or sourcing the addi-
tional charge required by the hold capacitor, CH, further reduc-
ing current transients seen at the op amp’s output.
The effect of this increased capacitive load on the op amp driv-
ing the AD9243 should be evaluated. To optimize performance
when noise is the primary consideration, increase the shunt
capacitance as much as the transient response of the input signal
will allow. Increasing the capacitance too much may adversely
affect the op amp’s settling time, frequency response, and dis-
tortion performance.
Table I. Analog Input Configuration Summary
Input
Connection
Single-Ended
Input
Coupling Span (V)
DC 2
Input Range (V)
VINA1
VINB1
0 to 2
1
Figure
#
32, 33
Comments
Best for stepped input response applications, suboptimum
THD and noise performance, requires ± 5 V op amp.
2 × VREF 0 to
2 × VREF
VREF
32, 33
5
0 to 5
2.5
32, 33
Single-Ended
Differential
AC
AC or
DC
2 × VREF
2 or
2 × VREF
5
2 × VREF
2
2.5 – VREF
to
2.5 + VREF
2.5
0 to 1 or
1 or VREF
0 to 2 × VREF
0 to 5
2.5
2.5 – VREF
to
2.5 + VREF
2.5
2 to 3
3 to 2
39
34
34
35
29–31
2 × VREF
5
2.5 – VREF/2
to
2.5 + VREF/2
1.75 to 3.25
2.5 + VREF/2
to
2.5 – VREF/2
3.25 to 1.75
29–31
29–31
NOTE
1VINA and VINB can be interchanged if signal inversion is required.
Same as above but with improved noise performance due to
increase in dynamic range. Headroom/settling time require-
ments of ± 5 op amp should be evaluated.
Optimum noise performance, excellent THD performance. Requires
op amp with VCC > +5 V due to insufficient headroom @ 5 V.
Optimum THD performance with VREF = 1, noise performance
improves while THD performance degrades as VREF increases
to 2.5 V. Single supply operation (i.e., +5 V) for many op amps.
Suboptimum ac performance due to input common-mode
level not biased at optimum midsupply level (i.e., 2.5 V).
Optimum noise performance, excellent THD performance.
Flexible input range, Optimum THD performance with
VREF = 1. Noise performance improves while THD perfor-
mance degrades as VREF increases to 2.5 V.
Optimum full-scale THD and SFDR performance well be-
yond the A/Ds Nyquist frequency.
Same as 2 V to 3 V input range with the exception that full-scale
THD and SFDR performance can be traded off for better noise
performance.
Widest dynamic range (i.e., ENOBs) due to Optimum Noise
performance.
–10–
REV. A
11 Page | ||
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| PDF Descargar | [ Datasheet AD9243.PDF ] | |
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