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PDF AD9244 Data sheet ( Hoja de datos )
| Número de pieza | AD9244 | |
| Descripción | 14-Bit 40/65 MSPS Monolithic A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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14-Bit, 40 MSPS/65 MSPS A/D Converter
AD9244
FEATURES
14-bit, 40 MSPS/65 MSPS ADC
Low power
550 mW at 65 MSPS
300 mW at 40 MSPS
On-chip reference and sample-and-hold
750 MHz analog input bandwidth
SNR > 73 dBc to Nyquist @ 65 MSPS
SFDR > 86 dBc to Nyquist @ 65 MSPS
Differential nonlinearity error = ±0.7 LSB
Guaranteed no missing codes over full temperature range
1 V to 2 V p-p differential full-scale analog input range
Single 5 V analog supply, 3.3 V/5 V driver supply
Out-of-range indicator
Straight binary or twos complement output data
Clock duty cycle stabilizer
Output-enable function
48-lead LQFP package
APPLICATIONS
Communication subsystems (microcell, picocell)
Medical and high-end imaging equipment
Test and measurement equipment
GENERAL DESCRIPTION
The AD9244 is a monolithic, single 5 V supply, 14-bit,
40 MSPS/65 MSPS ADC with an on-chip, high performance
sample-and-hold amplifier (SHA) and voltage reference.
The AD9244 uses a multistage differential pipelined architec-
ture with output error correction logic to provide 14-bit
accuracy at 40 MSPS/65 MSPS data rates, and guarantees no
missing codes over the full operating temperature range.
The AD9244 has an on-board, programmable voltage reference.
An external reference can also be used to suit the dc accuracy
and temperature drift requirements of the application.
A differential or single-ended clock input controls all internal
conversion cycles. The digital output data can be presented in
straight binary or in twos complement format. An out-of-range
(OTR) signal indicates an overflow condition that can be used
with the most significant bit to determine low or high overflow.
FUNCTIONAL BLOCK DIAGRAM
AVDD
REFT REFB
DRVDD
AD9244
VIN+
VIN–
SHA
10-STAGE 14
PIPELINE ADC
DFS
CLK+
CLK–
TIMING
OUTPUT
REGISTER
OTR
DCS
REFERENCE
14
D13 TO D0
OEB
AGND CML
VR VREF SENSE REF DGND
GND
Figure 1.
Fabricated on an advanced CMOS process, the AD9244 is
available in a 48-lead LQFP and is specified for operation over
the industrial temperature range (–40°C to +85°C).
PRODUCT HIGHLIGHTS
1. Low Power—The AD9244, at 550 mW, consumes a fraction
of the power of currently available ADCs in existing high
speed solutions.
2. IF Sampling—The AD9244 delivers outstanding
performance at input frequencies beyond the first Nyquist
zone. Sampling at 65 MSPS with an input frequency of
100 MHz, the AD9244 delivers 71 dB SNR and 86 dB SFDR.
3. Pin Compatibility—The AD9244 offers a seamless
migration from the 12-bit, 65 MSPS AD9226.
4. On-Board Sample-and-Hold (SHA)—The versatile SHA
input can be configured for either single-ended or
differential inputs.
5. Out-of-Range (OTR) Indicator—The OTR output bit
indicates when the input signal is beyond the AD9244’s
input range.
6. Single Supply—The AD9244 uses a single 5 V power
supply, simplifying system power supply design. It also
features a separate digital output driver supply to
accommodate 3.3 V and 5 V logic families.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
1 page  
AD9244
AC SPECIFICATIONS
AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS (–65) or 40 MSPS (–40), differential clock inputs, VREF = 2 V, external reference,
AIN = –0.5 dBFS, differential analog inputs, unless otherwise noted.
Table 2.
Parameter
SNR1
fIN = 2.4 MHz
fIN = 15.5 MHz (–1 dBFS)
fIN = 20 MHz
fIN = 32.5 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 200 MHz
SINAD1
fIN = 2.4 MHz
fIN = 20 MHz
fIN = 32.5 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 200 MHz
ENOB
fIN = 2.4 MHz
fIN = 20 MHz
fIN = 32.5 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 200 MHz
THD1
fIN = 2.4 MHz
fIN = 20 MHz
fIN = 32.5 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 200 MHz
Temp
Full
25°C
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
Test
Level
VI
I
IV
V
VI
I
IV
I
IV
V
V
V
VI
I
VI
I
IV
I
IV
V
V
V
VI
I
VI
I
IV
I
IV
V
V
V
VI
I
VI
I
IV
I
IV
V
V
V
AD9244BST-65
Min Typ
Max
72.4
74.8
72.0
73.7
70.8
73.0
69.9
72.2
71.2
67.2
72.2
74.7
70.6
72.6
69.7
71.9
71
59.8
11.7
12.1
11.4
11.8
11.3
11.7
11.5
9.6
−90.0
−78.4
−84.6
−84.1
−83.0
−60.7
−79.2
−78.7
AD9244BST-40
Min Typ
Max
73.4
75.3
72.1
74.7
72.8
68.3
73.2
75.1
72
74.4
72.4
56.3
11.9
12.2
11.7
12.1
11.7
9.1
−89.7
−89.4
−80.7
−80.4
−83.2
−56.6
Unit
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Rev. C | Page 4 of 36
5 Page 
AD9244
Spurious-Free Dynamic Range (SFDR)1
The difference in dB between the rms amplitude of the input
signal and the peak spurious signal.
Temperature Drift
The temperature drift for offset error and gain error specifies
the maximum change from initial (25°C) value to the value at
TMIN or TMAX.
Total Harmonic Distortion (THD)1
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal.
Offset Error
The major carry transition should occur for an analog value
½ LSB below VIN+ = VIN−. Offset error is defined as the
deviation of the actual transition from that point.
1 AC specifications can be reported in dBc (degrades as signal levels are
lowered) or in dBFS (always related back to converter full scale).
Rev. C | Page 10 of 36
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9244.PDF ] | |
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