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PDF AD6426 Data sheet ( Hoja de datos )
| Número de pieza | AD6426 | |
| Descripción | Enhanced GSM Processor | |
| Fabricantes | Analog Devices | |
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a Enhanced GSM Processor
Preliminary Technical Information
AD6426
FEATURES
Complete Single Chip GSM Processor
Channel Codec Subsystem including
Channel Coder/Decoder
Interleaver/De-interleaver
Encryption/Decryption
Control Processor Subsystem including
16-bit Control Processor (H8/300H)
Parallel and Serial Display Interface
Keypad Interface
EEPROM Interface
SIM-Interface
Universal System Connector Interface
Interface to AD6425
Control of Radio Subsystem
Programmable backlight duty cycle
Real Time Clock with Alarm
Battery ID Chip Interface
DSP Subsystem including
16-bit DSP with ROM coded firmware for
Full rate Speech Encoding/Decoding (GSM 06.10)
Enhanced Full Rate Speech
Encoding/Decoding (GSM 06.60)
Equalization with 16-state Viterbi (Soft Decision)
DTMF and Call Progress Tone Generation
Power Management of Mobile Radio
Slow Clocking scheme for low Idle Mode current
Ultra Low Power Design
On-chip GSM Data Services up to 14.4 kbit/s
JTAG Test Interface
2.4V to 3.3V Operating Voltage
144-Lead LQFP and 144-Lead PBGA packages
APPLICATIONS
GSM 900 / DCS1800 / PCS1900 Mobile Stations (MS)
Compliant to Phase 1 and Phase 2 specifications
GENERAL DESCRIPTION
The AD6426 Enhanced GSM Processor (EGSMP) is the
central component of the highly integrated AD20msp425 GSM
Chipset. Offering a low total chip count, low bill of materials
cost and long talk and standby times, the chipset offers
designers a straightforward route to a highly competitive
product in the GSM/DCS1800 market.
The EGSMP performs all the baseband functions of the Layer
1 processing of the GSM air interface. This includes all data
encoding and decoding processes as well as timing and radio
sub-system control functions.
The EGSMP supports full rate and enhanced full rate speech
traffic as well as a full range of data services including F14.4.
UNIVERSAL
SYSTEM CONN.
INTERFACE
TEST
INTERFACE
SIM
INTERFACE
EEPROM
INTERFACE
CHANNEL
CODEC
DSP
CHANNEL
EQUALIZER
SPEECH
CODEC
MEMORY
INTERFACE
CONTROL
PROCESSOR
VOICEBAND /
BASEBAND
CODEC
INTERFACE
DISPLAY
INTERFACE
RADIO
INTERFACE
ACCESSORY
INTERFACE
KEYPAD /
BACKLIGHT
INTERFACE
Figure 1. Functional Block Diagram
In addition, the EGSMP supports both A5/1 and A5/2
encryption algorithms as well as operation in non-encrypted
mode.
The EGSMP integrates a high performance 16-bit
microprocessor (Hitachi H8/300H), that supports all the GSM
terminal software, including Layer 1, 2 and 3 of the GSM
protocol stack, the MMI and applications software such as
data services, test and maintenance.
The use of the standard H8 processor allows the use of HIOS,
the Hitachi real time kernel, as well as a full range of software
development tools including C compilers, debuggers and in-
circuit emulators. The EGSMP also integrates a high
performance 16-bit Digital Signal Processor (DSP), which
provides speech transcoding and supports all audio functions
in both transmit and receive. In receive it equalizes the
received signal using a 16-state (Viterbi) soft decision
equalizer.
The EGSMP interfaces with all the peripheral sub-systems of
the terminal, including the keypad, memories, display driver,
SIM, DTE and DTA data services interface and radio. It also
has a general purpose interface that can be used to support an
external connection to a car kit or battery charger.
The EGSMP interfaces with the AD6425 or the AD6421
Voiceband/Baseband Codec through a dedicated serial port.
ORDERING GUIDE
Model
Temperature Range Package
AD6426XST
-25°C to +85°C 144-Lead LQFP
AD6426XB
-25°C to +85°C 144-Lead PBGA
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Revision Preliminary 2.3 (June 9, ´98)
-1-
Confidential Information
1 page  
Preliminary Technical Information
AD6426
Group
EVBC Interface
ASPORT
BSPORT
VSPORT
Radio Interface
Universal
System
Connector
Interface
Pin Name
CLKOUT
EVBCRESET
ASDO
ASOFS
ASCLK
ASDI
BSDO
BSOFS
BSCLK
BSDI
BSIFS
VSDO
VSDI
VSCLK
VSFS
RXON
TXPHASE
TXENABLE
TXPA
CALIBRATERADIO
RADIOPWRCTL
SYNTHEN0
SYNTHEN1
SYNTHDATA
SYNTHCLK
AGCA
AGCB
USCRI
USCRX
USCTX
USCCTS
USCRTS
Pin Functionality ( NORMAL MODE)
Pins I/O Default / Alternative Function(s) *
1 O Clock Output to EVBC
1 O EVBC Reset Output (also for Display reset)
1 O EVBC Auxiliary Serial Port Data Output
1 O EVBC Auxiliary Serial Port Output Framing Signal
1 O EVBC Auxiliary Serial Port Clock Output
1 I EVBC Auxiliary Serial Port Data Input
1 O EVBC Baseband Serial Port Data Output
1 O EVBC Baseband Serial Port Output Framing Signal
1 I EVBC Baseband Serial Port Clock Input
1 I EVBC Baseband Serial Port Data Input
1 I EVBC Baseband Serial Port Input Framing Signal
1 O EVBC Voiceband Serial Port Data Output
1 I EVBC Voiceband Serial Port Data Input
1 I EVBC Voiceband Serial Port Clock Input
1 I EVBC Voiceband Serial Port Framing Signal
1 O Receiver On
1 O Switches between Rx and Tx
1 O Transmit Enable / General Purpose Output 14 *
1 O / O Power Amplifier Enable / General Purpose Output 12 *
1 O / O Radio Calibration / General Purpose Output 13 *
1 O Radio Power-Down Control
1 O Synthesizer 1 Enable
1 O Synthesizer 2 Enable / General Purpose Output 17 *
1 O RF Serial Port Data
1 O RF Serial Port Clock
1 O AGC Gain Select / General Purpose Output 18
1 O AGC Gain Select / General Purpose Output 19
1 1/O USC Ring Indicator / Serial Clock / GPO20
1 I USC Receive Data
1 O USC Transmit Data / Baseband Serial Port Data Input
1 I/O USC Clear to Send / Serial Frame Sync / GPI22
1 O USC Ready to Send / GPO21
* Note: Functionality of these pins can be changed under software control.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Revision Preliminary 2.3 (June 9, ´98)
-5-
Confidential Information
5 Page 
Preliminary Technical Information
AD6426
Table 3. H8 Peripheral Control Registers
Address
0 8000h
1 8001h
2 8002h
3 8003h
4 8004h
5 8005h
6 8006h
10 8010h
10 8010h
10 8010h
11 8011h
11 8011h
12 8012h
12 8012h
13 8013h
14 8014h
15 8015h
16 8016h
17 8017h
18 8018h
18 8018h
19 8019H
26 801AH
27 801BH
28 801CH
29 801Dh
32 8020h
32 8020h
32 8020h
33 8021h
33 8021h
34 8022h
35 8023h
36 8024h
37 8025h
38 8026h
39 8027h
48 8030h
49 8031h
50 8032h
51 8033h
52 8034h
53 8035h
Name
SMSMR
SMBRR
SMSCR
SMDR
SMSSR
SMDR
SMSCMR
BUFRBR
BUFTHR
BUFDLL
BUFIER
BUFDLM
BUFIIR
BUFFCR
BUFLCR
BUFMCR
BUFLSR
BUFMSR
BUFSCR
UIBRBR
UIBTHR
UIBSSR
UIBER
UIBTSR
UIBTLR
UIBBLR
FIXRBR
FIXTHR
FIXDLL
FIXIER
FIXDLM
FIXIIR
FIXLCR
FIXMCR
FIXLSR
FIXMSR
FIXSCR
SCCR
SPSSR
SDIR1 (MS)
SDIR0 (LS)
SDOR1 (MS)
SDOR0 (LS)
R/W
R/W
R/W
W
R/W
R
R/W
R
W
R/W
R/W
R/W
R
W
R/W
R/W
R/W
R/W
R/W
R
W
R/W
R
R
R/W
R
R
W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
W
W
Address
64/65 8040/1h
66 8042h
67 8043h
68 8044h
69 8045h
72 8048h
80 8050h
81 8051h
82 8052h
84 8054h
85 8055h
96 8060h
97 8061h
98 8062h
99 8063h
100 8064h
101 8065h
102 8066h
103 8067h
104 8068h
105 8069h
106 8074h
Name
DISPDDR
DISPCR
DDOR
DDIR
DRR
WDTR
MEM IF
PERST
PERCR
TAR
PERCLK
RTCTR1
RTCTR2
RTCTR3
RTCTR4
RTCTR5
RTCAR1
RTCAR2
RTCAR3
RTCCR
RTCSRZ
SERDISPLAY/NMI
W
R/W
W
R
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Revision Preliminary 2.3 (June 9, ´98)
- 11 -
Confidential Information
11 Page | ||
| Páginas | Total 50 Páginas | |
| PDF Descargar | [ Datasheet AD6426.PDF ] | |
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