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PDF AD6634 Data sheet ( Hoja de datos )
| Número de pieza | AD6634 | |
| Descripción | 80 MSPS/ Dual-Channel WCDMA Receive Signal Processor (RSP) | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD6634 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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a
80 MSPS, Dual-Channel WCDMA
Receive Signal Processor (RSP)
AD6634
FEATURES
80 MSPS Wideband Inputs (14 Linear Bits Plus Three
RSSI)
Processes Two WCDMA Channels (UMTS or CDMA2000
1؋) or Four GSM/EDGE, IS136 Channels
Four Independent Digital Receivers in a Single Package
Dual 16-Bit Parallel Output Ports
Dual 8-Bit Link Ports
Programmable Digital AGC Loops with 96 dB Range
Digital Resampling for Noninteger Decimation Rates
Programmable Decimating FIR Filters
Interpolating Half-Band Filters
Programmable Attenuator Control for Clip Prevention
and External Gain Ranging via Level Indicator
Flexible Control for Multicarrier and Phased Array
3.3 V I/O, 2.5 V CMOS Core
User Configurable Built-In Self-Test (BIST) Capability
JTAG Boundary Scan
APPLICATIONS
Multicarrier, Multimode Digital Receivers
GSM, IS136, EDGE, PHS, IS95, UMTS, CDMA2000
Micro and Pico Cell Systems, Software Radios
Wireless Local Loop
Smart Antenna Systems
In Building Wireless Telephony
INA[13:0]
EXPA[2:0]
IENA
LIA-A
LIA-B
INB[13:0]
EXPB[2:0]
IENB
LIB-A
LIB-B
SYNCA
SYNCB
SYNCC
SYNCD
I
N
P
U
T
M
A
T
R
I
X
EXTERNAL
SYNC.
CIRCUIT
FUNCTIONAL BLOCK DIAGRAM
rCIC2
RESAMPLER
CIC5
NCO
rCIC2
RESAMPLER
CIC5
NCO
rCIC2
RESAMPLER
CIC5
NCO
rCIC2
RESAMPLER
CIC5
NCO
JTAG
RAM
COEFFICIENT
FILTER
CHANNEL 0
RAM
COEFFICIENT
FILTER
CHANNEL 1
RAM
COEFFICIENT
FILTER
CHANNEL 2
RAM
COEFFICIENT
FILTER
CHANNEL 3
RCF OUTPUTS
CHANNELS 0, 1, 2, 3
INTERPOLATING
HALF-BAND FILTER
PLUS
DIGITAL AGC
INTERPOLATING
HALF-BAND FILTER
PLUS
DIGITAL AGC
RCF OUTPUTS
CHANNELS 0, 1, 2, 3
PORT A
LINK PORT
OR
PARALLEL
PORT
OUTPUT
MUX
CIRCUITRY
PORT B
LINK PORT
OR
PARALLEL
PORT
BUILT-IN (BIST)
SELF-TEST CIRCUITRY
MICROPORT OR SERIAL
PORT CONTROL
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
1 page  
WIDEBAND INPUT SPECTRUM (؊fSAMPLE/2 TO fSAMPLE/2)
SIGNAL OF INTEREST “IMAGE”
AD6634
SIGNAL OF INTEREST
–fS/2
–3fS/8 –5fS/16
–fS/4
–3fS/16
–fS/8
–fS/16
dc
fS/16
fS/8 3fS/16
WIDEBAND INPUT SPECTRUM (e.g., 30MHz FROM HIGH SPEED ADC)
fS/4 5fS/16 3fS/8
fS/2
AFTER FREQUENCY TRANSLATION
NCO “TUNES” SIGNAL TO BASEBAND
–fS/2
–3fS/8 –5fS/16
–fS/4
–3fS/16
–fS/8
–fS/16
dc
fS/16
fS/8 3fS/16 fS/4
FREQUENCY TRANSLATION (e.g., SINGLE 1MHz CHANNEL TUNED TO BASEBAND)
Figure 1a. Frequency Translation of Wideband Input Spectrum
5fS/16
3fS/8
fS/2
20
0
–20
–40
–60
–80
–100
–120
–1.5؋104
–1.0؋104
–5000
0
kHz
5000
1.0؋104
Figure 1b. Composite Filter Response of rCIC2, CIC5, and RCF
1.5؋104
REV. 0
–5–
5 Page 
CLK
SYNCA
SYNCB
SYNCC
CYNCD
tSS tHS
Figure 7. SYNC Timing Inputs
AD6634
CLK
tDPOCLKL
PCLK
Figure 8. PCLK to CLK Switching Characteristics Divide by 1
CLK
tDPOCLKLL
PCLK
tPOCLKH
tPOCLKL
Figure 9. PCLK to CLK Switching Characteristics Divide by 2, 4, or 8
PCLK
PxACK
tSPA
tHPA
Figure 10. Master Mode PxACK to PCLK Setup and Hold Characteristics
REV. 0
–11–
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD6634.PDF ] | |
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