PDF AD724 Data sheet ( Hoja de datos )

Número de pieza	AD724
Descripción	RGB to NTSC/PAL Encoder
Fabricantes	Analog Devices
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No Preview Available ! a RGB to NTSC/PAL Encoder AD724 FEATURES Low Cost, Integrated Solution +5 V Operation Accepts FSC Clock or Crystal, or 4FSC Clock Composite Video and Separate Y/C (S-Video) Outputs Luma and Chroma Outputs Are Time Aligned Minimal External Components: No External Filters or Delay Lines Required Onboard DC Clamp Accepts Either HSYNC and VSYNC or CSYNC Phase Lock to External Subcarrier Drives 75 ⍀ Reverse-Terminated Loads Logic Selectable NTSC or PAL Encoding Modes Compact 16-Lead SOIC APPLICATIONS RGB to NTSC or PAL Encoding PRODUCT DESCRIPTION The AD724 is a low cost RGB to NTSC/PAL Encoder that converts red, green and blue color component signals into their corresponding luminance (baseband amplitude) and chromi- nance (subcarrier amplitude and phase) signals in accordance with either NTSC or PAL standards. These two outputs are also combined to provide composite video output. All three outputs can simultaneously drive 75 Ω, reverse-terminated cables. All logi- cal inputs are TTL, 3 V and 5 V CMOS compatible. The chip operates from a single +5 V supply. No external delay lines or filters are required. The AD724 may be powered down when not in use. The AD724 accepts either FSC or 4FSC clock. When a clock is not available, a low cost parallel-resonant crystal (3.58 MHz (NTSC) or 4.43 MHz (PAL)) and the AD724’s on-chip oscilla- tor generate the necessary subcarrier clock. The AD724 also accepts the subcarrier clock from an external video source. The interface to graphics controllers is simple: an on-chip logic “XNOR” accepts the available vertical (VSYNC) and horizon- tal sync (HSYNC) signals and creates the composite sync (CSYNC) signal on-chip. If available, the AD724 will also accept a standard CSYNC signal by connecting VSYNC to Logic HI and applying CSYNC to the HSYNC pin. The AD724 contains decoding logic to identify valid horizontal sync pulses for correct burst insertion. Delays in the U and V chroma filters are matched by an on-chip sampled-data delay line in the Y signal path. To prevent alias- ing, a prefilter at 5 MHz is included ahead of the delay line and a post-filter at 5 MHz is added after the delay line to suppress harmonics in the output. These low-pass filters are optimized for minimum pulse overshoot. The overall luma delay, relative to chroma, has been designed to be time aligned for direct input to a television’s baseband. The AD724 comes in a space-saving SOIC and is specified for the 0°C to +70°C commercial tem- perature range. FUNCTIONAL BLOCK DIAGRAM SUB- CARRIER FSC 4FSC NTSC/PAL HSYNC VSYNC 4FSC XNOR 4FSC XOSC PHASE DETECTOR CHARGE PUMP SYNC SEPARATOR CSYNC QUADRATURE +4 DECODER FSC CSYNC BURST FSC 90° FSC 0° CSYNC LOOP FILTER 4FSC VCO NTSC/PAL ±180° SC 90°/270° (PAL ONLY) CLOCK AT 8FSC RED GREEN BLUE DC CLAMP DC CLAMP DC CLAMP Y 3-POLE LP PRE- FILTER RGB-TO-YUV ENCODING MATRIX U 4-POLE LPF V 4-POLE LPF U CLAMP V CLAMP SAMPLED- DATA DELAY LINE 2-POLE LP POST- FILTER NTSC/PAL BALANCED MODULATORS 4-POLE LPF X2 LUMINANCE OUTPUT X2 COMPOSITE OUTPUT X2 CHROMINANCE OUTPUT BURST REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 1 page Typical Performance Characteristics–AD724 TEKTRONIX TSG 300 COMPONENT VIDEO WAVEFORM GENERATOR COMPOSITE SYNC RGB 3 GENLOCK 75⍀ TEKTRONIX 1910 COMPOSITE VIDEO WAVEFORM GENERATOR FSC +5V AD724 RGB TO NTSC/PAL ENCODER FIN COMPOSITE VIDEO SONY MONITOR MODEL 1342 75⍀ TEKTRONIX VM700A WAVEFORM MONITOR Figure 1. Evaluation Setup 1.0 APL = 49.8% 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00V @ 6.63␮s 0.5 100 50 0.0 0 SYNCHRONOUS SYNC = SOURCE FRAMES SELECTED : 1 2 –50 –0.5 0 10 20 30 40 50 60 ␮s Figure 2. Modulated Pulse and Bar, NTSC 1.0 APL = 50.0% 625 LINE PAL NO FILTERING SLOW CLAMP TO 0.00V @ 6.72␮s 0.5 0.0 ASYNCHRONOUS SYNC = SOURCE FRAMES SELECTED : 1 2 3 4 –0.5 0 10 20 30 40 50 60 ␮s Figure 3. Modulated Pulse and Bar, PAL 1.0 APL = 50.8% 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00V @ 6.63␮s 100 0.5 50 0.0 0 –0.5 0 PRECISION MODE OFF SYNCHRONOUS SYNC = SOURCE FRAMES SELECTED : 1 2 –50 10 20 30 40 50 60 ␮s Figure 4. 100% Color Bars, NTSC 1.0 APL = 50.6% 625 LINE PAL NO FILTERING SLOW CLAMP TO 0.00V @ 6.72␮s 0.5 0.0 –0.5 0 ASYNCHRONOUS SYNC = SOURCE FRAMES SELECTED : 1 2 3 4 10 20 30 40 50 ␮s Figure 5. 100% Color Bars, PAL 60 REV. B –5– 5 Page AD724 +5V (VAA) 0.1␮F VAA COMP 24 DATA IN VREF FSADJ +5V (VAA) ADV7120 10k⍀ MPEG DECODER SYNC CLOCK BLANK GND IOR IOG IOB 0.01␮F 0.1␮F +5V 0.1␮F 0.1␮F 0.01␮F +5V 10k⍀ RSET 550⍀ AD589 (1.2V REF) +5V 10k⍀ *** 0.1␮F 0.1␮F 75⍀ 75⍀ 75⍀ 75⍀ 75⍀ 75⍀ 0.1␮F APOS ENCD DPOS AD724 SELECT COMP RIN GIN LUMA BIN HSYNC VSYNC +5V * PARALLEL–RESONANT CRYSTAL; 3.579545MHz (NTSC) OR 4.433620MHz (PAL) CAPACITOR VALUE DEPENDS 0.1␮F ON CRYSTAL CHOSEN FSC OR 4FSC CLOCK; 3.579545MHz, 14.31818MHz (NTSC) OR 4.433620MHz, 17.734480MHz(PAL) * 0.1␮F CAPACITORS RECOMMENDED OSC ** * CRYSTAL HSYNC VSYNC 10–30pF HSYNC VSYNC CRMA FIN DGND STND AGND +5V (VAA) +5V (VCC) L1 (FERRITE BEAD) 10␮F 33␮F GND 75⍀ 220␮F 75⍀ 220␮F 75⍀ 220␮F +5V 10k⍀ COMPOSITE VIDEO S-VIDEO Figure 16. AD724 and ADV7120/ADV7122 Providing MPEG Video Solution Figure 15 shows a circuit for connection to the VGA port of a PC. The RGB outputs are ac coupled to the respective inputs of the AD724. These signals should each be terminated to ground with 75 Ω. The standard 15-pin VGA connector has HSYNC on Pin 13 and VSYNC on Pin 14. These signals also connect directly to the same name signals on the AD724. The FIN signal can be provided by any of the means described elsewhere in the data sheet. For a synchronous NTSC system, the internal 4FSC (14.31818 MHz) clock that drives the VGA controller can be used for FIN on the AD724. This signal is not directly accessible from outside the computer, but it does appear on the VGA card. If a separate RGB monitor is also to be used, it is not possible to simply connect it to the R, G and B signals. The monitor pro- vides a termination that would double terminate these signals. The R, G and B signals should be buffered by three amplifiers with high input impedances. These should be configured for a gain of two, which is normalized by the divide-by-two termina- tion scheme used for the RGB monitor. The AD8013 is a triple video amplifier that can provide the necessary buffering in a single package. It also provides a disable pin for each amplifier, which can be used to disable the drive to the RGB monitor when interlaced video is used (SELECT = LO). When the RGB signals are noninterlaced, setting SELECT HI will enable the AD8013 to drive the RGB monitor and disable the encoding function of the AD724 via Pin 5. HSYNC and VSYNC are logic level signals that can drive both the AD724 and RGB monitor in parallel. If the disable feature is not required, the AD8073 triple video op amp can provide a lower cost solution. AD724 Used with an MPEG Decoder MPEG decoding of compressed video signals is becoming a more prevalent feature in many PC systems. To display images on the computer monitor, video in RGB format is required. However, to display the images on a TV monitor, or to record the images on a VCR, video in composite format is required. Figure 16 shows a schematic for taking the 24-bit wide RGB video from an MPEG decoder and creating both analog RGB video and composite video. The 24-bit wide RGB video is converted to analog RGB by the ADV7120 (Triple 8-bit video DAC—available in 48-lead LQFP). The analog current outputs from the DAC are termi- nated to ground at both ends with 75 Ω as called for in the data sheet. These signals are ac coupled to the analog inputs of the AD724. The HSYNC and VSYNC signals from the MPEG Controller are directly applied to the AD724. If the set of termination resistors closest to the AD724 are re- moved, an RGB monitor can be connected to these signals and will provide the required second termination. This is acceptable as long as the RGB monitor is always present and connected. If it is to be removed on occasion, another termination scheme is required. The AD8013 or AD8073 triple video op amp can provide buff- ering for such applications. Each channel is set for a gain of two while the outputs are back terminated with a series 75 Ω resis- tor. This provides the proper signal levels at the monitor, which terminates the lines with 75 Ω. AD724 APPLICATION DISCUSSION—NTSC/PAL CRYSTAL SELECT CIRCUIT For systems that support both NTSC and PAL, and will use a crystal for the subcarrier, a low cost crystal selection circuit can be made that, in addition to the two crystals, requires two low cost diodes, two resistors and a logic inverter gate. The circuit selection can be driven by the STND signal that already drives Pin 1 to select between NTSC and PAL operation for the AD724. A schematic for such a circuit is shown in Figure 17. Each crys- tal ties directly to FIN (Pin 3) with one terminal and has the other terminal connected via a series diode to ground. Each diode serves as a switch, depending on whether it is forward biased or has no bias. REV. B –11– 11 Page

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