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PDF AD5203 Data sheet ( Hoja de datos )
| Número de pieza | AD5203 | |
| Descripción | 4-Channel/ 64-Position Digital Potentiometer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
4-Channel, 64-Position
Digital Potentiometer
AD5203
FEATURES
64 Position
Replaces Four Potentiometers
10 k⍀, 100 k⍀
Power Shutdown—Less than 5 A
3-Wire SPI-Compatible Serial Data Input
10 MHz Update Data Loading Rate
+2.7 V to +5.5 V Single Supply Operation
Midscale Preset
APPLICATIONS
Mechanical Potentiometer Replacement
Programmable Filters, Delays, Time Constants
Volume Control, Panning
Line Impedance Matching
Power Supply Adjustment
GENERAL DESCRIPTION
The AD5203 provides a quad channel, 64-position digitally-
controlled variable resistor (VR) device. These parts perform the
same electronic adjustment function as a potentiometer or vari-
able resistor. The AD5203 contains four independent variable
resistors in a 24-lead SOIC and the compact TSSOP-24 pack-
ages. Each part contains a fixed resistor with a wiper contact
that taps the fixed resistor value at a point determined by a digi-
tal code loaded into the controlling serial input register. The
resistance between the wiper and either endpoint of the fixed
resistor varies linearly with respect to the digital code transferred
into the VR latch. Each variable resistor offers a completely
programmable value of resistance, between the A terminal and
the wiper or the B terminal and the wiper. The fixed A-to-B
terminal resistance of 10 kΩ, or 100 kΩ has a ± 1% channel-to-
channel matching tolerance with a nominal temperature coeffi-
cient of 700 ppm/°C.
Each VR has its own VR latch which holds its programmed
resistance value. These VR latches are updated from an internal
serial-to-parallel shift register that is loaded from a standard
3-wire serial-input digital interface. Eight data bits make up the
data word clocked into the serial input register. The data word is
decoded where the first two bits determine the address of the VR
latch to be loaded, the last 6-bits are data. A serial data output
pin at the opposite end of the serial register allows simple daisy-
chaining in multiple VR applications without additional external
decoding logic.
FUNCTIONAL BLOCK DIAGRAM
VDD
DGND
SDI
CLK
CS
AD5203
1
DAC 2
SELECT
3
4
A1, A0
2
8-BIT
SERIAL
LATCH
6
D
CK Q RS
6-BIT
LATCH
6
CK RS
DAC 1
SHDN
A1
W1
B1
AGND1
6-BIT
LATCH
6
CK RS
DAC 2
SHDN
A2
W2
B2
AGND2
6-BIT
LATCH
6
CK RS
DAC 3
SHDN
A3
W3
B3
AGND3
6-BIT
LATCH
6
CK RS
DAC 4
SHDN
A4
W4
B4
AGND4
SDO
RS
SHDN
The reset RS pin forces the wiper to the midscale position by
loading 20H into the VR latch. The SHDN pin forces the resis-
tor to an end-to-end open circuit condition on terminal A and
shorts the wiper to terminal B, achieving a microwatt power
shutdown state. When shutdown is returned to logic-high the
previous latch settings put the wiper in the same resistance set-
ting prior to shutdown.
The AD5203 is available in a narrow body P-DIP-24, the
24-lead surface mount package, and the compact 1.1 mm thin
TSSOP-24 package. All parts are guaranteed to operate over the
extended industrial temperature range of –40°C to +85°C.
For pin compatible higher resolution applications, see the 256-
position AD8403 product.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
1 page  
10
9
VDD = +3V, OR +5V
RAB = 10k⍀
8
7
6
5
4
3
RWB
RWA
2
1
0
0 8 16 24 32 40 48 56 64
CODE – Decimal
Figure 2. Wiper to End Terminal
␣ ␣ Resistance vs. Code
Typical Performance Characteristics– AD5203
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0
3FH
20H
10H
08H
05H
02H
RAB = 10k⍀
VDD = +5V
TA = +25؇C
1234567
IWA CURRENT – mA
Figure 3. Resistance Linearity vs.
␣ ␣ Conduction Current
0.25
0.2
0.15
0.1
0.05
0
–0.05
–0.1
–0.15
–0.2
–0.25
0
VDD = +3.0V
TA = +85؇C
TA = –55؇C TA = +25؇C
8 16 24 32 40 48 56 64
DIGITAL INPUT CODE – Decimal
Figure 4. Resistance Step Position
␣ ␣ Nonlinearity Error vs. Code
80
SS = 544 UNITS
VDD = +4.5V
TA = +25؇C
60
40
20
0
30 31 32 33 34 35 36 37 38 39
WIPER RESISTANCE – ⍀
Figure 5.␣ Wiper-Contact-Resistance
Histogram
12
AD5203-10K VERSION
10
RAB (END-TO-END)
8
6
4
RWB (WIPER-TO-END)
CODE = 20H
2
0
–75 –50 –25 0 25 50 75 100 125
TEMPERATURE – ؇C
␣ ␣ Figure 6.␣ Nominal Resistance vs.
␣ ␣ Temperature
0.25
0.2
0.15
0.1
0.05
0
–0.05
–0.1
–0.15
–0.2
–0.25
0
VDD = +3.0V
+25؇C
–55؇C
+85؇C
8 16 24 32 40 48 56 64
DIGITAL INPUT CODE – Decimal
␣ ␣ ␣ Figure 7. Potentiometer Divider
␣ ␣ Nonlinearity Error vs. Code
0.25
0.2
0.15
VDD = +3.0V
TA = +25؇C, +85؇C, –40؇C
0.1
0.05
0
–0.05
–0.1
–0.15
–0.2
–0.25
0
8 16 24 32 40 48 56 64
DIGITAL INPUT CODE – Decimal
Figure 8. Potentiometer Divider
Differential Nonlinearity Error vs.
Code
50
VDD = +3.0V
TA = –40؇C/+85؇C
40 VA = +2.0V
VB = 0V
30
20
10
0
0 8 16 24 32 40 48 56 64
CODE – Decimal
Figure 9.␣ ∆VWB/∆T Potentiometer
Mode Tempco
120
VDD = +3.0V
100
TA = –40؇C/+85؇C
VA = NO CONNECT
RWB MEASURED
80
60
40
20
0
0 8 16 24 32 40 48 56 64
CODE – Decimal
Figure 10. ∆RWB/∆T Rheostat Mode
Tempco
REV. 0
–5–
5 Page 
The data setup and data hold times in the specification table
determine the data valid time requirements. The last eight bits
of the data word entered into the serial register are held when
CS returns high. At the same time CS goes high it gates the
address decoder which enables one of four positive edge trig-
gered RDAC latches, see Figure 36 detail.
AD5203
CS
CLK
SDI
ADDR
DECODE
RDAC 1
RDAC 2
RDAC 4
SERIAL
REGISTER
Figure 36. Equivalent Input Control Logic
The target RDAC latch is loaded with the last six bits of the
serial data word completing one RDAC update. Four separate
8-bit data words must be clocked in to change all four VR
settings.
SHDN
CS
SDI
CLK
RS
SERIAL
REGISTER
DQ
CK RS
SDO
Figure 37. Detail, SDO Output Schematic of the AD5203
AD5203
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 38. Applies to
digital input pins CS, SDI, SDO, RS, SHDN, CLK.
1k⍀
LOGIC
Figure 38. Equivalent ESD Protection Circuit
DYNAMIC CHARACTERISTICS
The total harmonic distortion plus noise (THD+N) measures
0.003% using an offset ground with a rail-to-rail OP279 invert-
ing op amp test circuit, see Figure 30. Figure 15 plots THD
versus frequency for both inverting and noninverting amplifier
topologies. Thermal noise is primarily Johnson noise, typically
9 nV/√Hz for the 10 kΩ version measured at 1 kHz. For the
100 kΩ device, thermal noise measures 29 nV/√Hz. Channel-to-
channel crosstalk measures less than –65 dB at f = 100 kHz. To
achieve this isolation, the extra ground pins (AGND) located
between the potentiometer terminals (A, B, W) must be con-
nected to circuit ground. The AGND and DGND pins should
be at the same voltage potential. Any unused potentiometers in
a package should be connected to ground. Power supply rejec-
tion is typically –50 dB at 10 kHz (care is needed to minimize
power supply ripple injection in high accuracy applications).
REV. 0
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AD5203.PDF ] | |
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