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PDF AT25010 Data sheet ( Hoja de datos )
| Número de pieza | AT25010 | |
| Descripción | SPI Serial EEPROMs | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
• 3.0 MHz Clock Rate (5V)
• 8-byte Page Mode
• Block Write Protection
– Protect 1/4, 1/2, or Entire Array
• Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
• Self-timed Write Cycle (10 ms max)
• High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
• Automotive Grade Devices Available
• 8-lead PDIP and 8-lead JEDEC SOIC Packages
Description
The AT25010/020/040 provides 1024/2048/4096 bits of serial electrically erasable
programmable read only memory (EEPROM) organized as 128/256/512 words of 8
bits each. The device is optimized for use in many industrial and commercial applica-
tions where low-power and low voltage operation are essential. The AT25010/020/040
is available in space saving 8-lead PDIP and 8-lead JEDEC SOIC packages.
The AT25010/020/040 is enabled through the Chip Select pin (CS) and accessed via a
3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-
rate ERASE cycle is required before WRITE.
BLOCK WRITE protection is enabled by programming the status register with one of
four blocks of write protection. Separate program enable and program disable instruc-
tions are provided for additional data protection. Hardware data protection is provided
via the WP pin to protect against inadvertent write attempts. The HOLD pin may be
used to suspend any serial communication without resetting the serial sequence.
Pin Configurations
Pin Name
CS
SCK
Function
Chip Select
Serial Data Clock
SI
SO
GND
VCC
Serial Data Input
Serial Data Output
Ground
Power Supply
WP
HOLD
Write Protect
Suspends Serial Input
8-lead PDIP
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
8-lead SOIC
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
SPI Serial
EEPROMs
1K (128 x 8)
2K (256 x 8)
4K (512 x 8)
AT25010
AT25020
AT25040
Rev. 0606M–SEEPR–06/03
1
1 page  
Serial Interface
Description
AT25010/020/040
MASTER: The device that generates the serial clock.
SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25010/020/040
always operates as a slave.
TRANSMITTER/RECEIVER: The AT25010/020/040 has separate pins designated for
data transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
The op-code also contains address bit A8 in both the READ and WRITE instructions.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25010/020/040, and the serial output pin (SO) will remain in a high impedance state
until the falling edge of CS is detected again. This will reinitialize the serial
communication.
CHIP SELECT: The AT25010/020/040 is selected when the CS pin is low. When the
device is not selected, data will not be accepted via the SI pin, and the serial output pin
(SO) will remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the
AT25010/020/040. When the device is selected and a serial sequence is underway,
HOLD can be used to pause the serial communication with the master device without
resetting the serial sequence. To pause, the HOLD pin must be brought low while the
SCK pin is low. To resume serial communication, the HOLD pin is brought high while the
SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored
while the SO pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations
when held high. When the WP pin is brought low, all write operations are inhibited.
WP going low while CS is still low will interrupt a write to the AT25010/020/040. If the
internal write cycle has already been initiated, WP going low will have no effect on any
write operation.
0606M–SEEPR–06/03
5
5 Page 
AT25010/020/040
WRITE Timing
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
INSTRUCTION
BYTE ADDRESS
DATA IN
SI 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
9TH BIT OF ADDRESS
HIGH IMPEDANCE
SO
HOLD Timing
CS
SCK
HOLD
SO
tCD
tHD
tHZ
tCD
tHD
tLZ
0606M–SEEPR–06/03
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet AT25010.PDF ] | |
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