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PDF ADE7754 Data sheet ( Hoja de datos )
| Número de pieza | ADE7754 | |
| Descripción | Polyphase Multifunction Energy Metering IC | |
| Fabricantes | Analog Devices | |
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Polyphase Multifunction
Energy Metering IC with Serial Port
ADE7754
FEATURES
High Accuracy, Supports IEC 687/61036
Compatible with 3-Phase/3-Wire, 3-Phase/4-Wire
and any Type of 3-Phase Services
Less than 0.1% Error in Active Power Measurement over a
Dynamic Range of 1000 to 1
Supplies Active Energy, Apparent Energy, Voltage RMS,
Current RMS, and Sampled Waveform Data
Digital Power, Phase, and Input Offset Calibration
On-Chip Temperature Sensor (؎4؇C Typical after Calibration)
On-Chip User Programmable Thresholds for Line Voltage
SAG and Overdrive Detections
SPI Compatible Serial Interface with Interrupt
Request Line (IRQ)
Pulse Output with Programmable Frequency
Proprietary ADCs and DSP Provide High Accuracy over
Large Variations in Environmental Conditions and Time
Single 5 V Supply
GENERAL DESCRIPTION
The ADE7754 is a high accuracy polyphase electrical energy
measurement IC with a serial interface and a pulse output. The
ADE7754 incorporates second order Σ-∆ ADCs, reference
circuitry, temperature sensor, and all the signal processing
required to perform active, apparent energy measurements, and
rms calculation.
The ADE7754 provides different solutions for measuring active
and apparent energy from the six analog inputs, thus enabling
the use of the ADE7754 in various power meter services such as
3-phase/4-wire, 3-phase/3-wire, and 4-wire delta.
In addition to rms calculation, active and apparent power infor-
mation, the ADE7754 provides system calibration features for
each phase (i.e., channel offset correction, phase calibration,
and gain calibration). The CF logic output provides instanta-
neous active power information.
The ADE7754 has a waveform sample register that enables
access to ADC outputs. The part also incorporates a detection
circuit for short duration low or high voltage variations. The
voltage threshold levels and the duration (number of half line
cycles) of the variation are user programmable.
A zero-crossing detection is synchronized with the zero-crossing
point of the line voltage of each of the three phases. The infor-
mation collected is used to measure each line’s period. It is also
used internally to the chip in the line active energy and line
apparent energy accumulation modes. This permits faster and
more accurate calibration of the power calculations. This signal
is also useful for synchronization of relay switching.
Data is read from the ADE7754 via the SPI serial interface. The
interrupt request output (IRQ) is an open-drain, active low
logic output. The IRQ output goes active low when one or more
interrupt events have occurred in the ADE7754. A status regis-
ter indicates the nature of the interrupt.
The ADE7754 is available in a 24-lead SOIC package.
IAP
IAN
VAP
IBP
IBN
VBP
ICP
ICN
VCP
VN
REV. 0
PGA1
PGA2
ADC
ADC
PGA1
PGA2
ADC
ADC
PGA1
PGA2
ADC
ADC
4k⍀
2.4V REF
FUNCTIONAL BLOCK DIAGRAM
RESET
AVDD
AVGAIN
X2
AAPGAIN HPF
X2
⌽ APHCAL
BVGAIN
X2
BAPGAIN HPF
X2
⌽ BPHCAL
CVGAIN
X2
CAPGAIN HPF
X2
⌽ CPHCAL
AVRMSOS
AIRMSOS
AVAG
LPF2
AAPOS
BVRMSOS
BIRMSOS
|X|
AWG ABS
BVAG
LPF2
BAPOS
CVRMSOS
CIRMSOS
BWG
|X|
ABS
CVAG
LPF2
CAPOS
CWG
TEMP
SENSOR
|X|
ABS
ADC
POWER SUPPLY
MONITOR
ADE7754
CFNUM
،DFC
CFDEN
% WDIV % VADIV
ADE7754 REGISTERS AND
SERIAL INTERFACE
AGND
REFIN/OUT
DIN DOUT SCLK CS IRQ
CF
DVDD
DGND
CLKIN
CLKOUT
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
1 page  
ADE7754
TIMING CHARACTERISTICS1, 2 (AVDD = DVDD = 5 V ؎ 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10 MHz XTAL,
TMIN to TMAX = –40؇C to +85؇C, unless otherwise noted.)
Parameter
Spec
Unit
Test Conditions/Comments
Write Timing
t1
t2
t3
t4
t5
t6
t7
t8
Read Timing
t93
t10
t114
t125
t135
50
50
50
10
5
400
50
100
4
50
30
100
10
100
10
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
µs (min)
ns (min)
ns (min)
ns (max)
ns (min)
ns (max)
ns (min)
CS Falling Edge to First SCLK Falling Edge
SCLK Logic High Pulsewidth
SCLK Logic Low Pulsewidth
Valid Data Setup Time before Falling Edge of SCLK
Data Hold Time after SCLK Falling Edge
Minimum Time between the End of Data Byte Transfers
Minimum Time between Byte Transfers during a Serial Write
CS Hold Time after SCLK Falling Edge
Minimum Time between Read Command (i.e., a Write to Communication
Register) and Data Read
Minimum Time between Data Byte Transfers during a Multibyte Read
Data Access Time after SCLK Rising Edge following a Write to the
Communications Register
Bus Relinquish Time after Falling Edge of SCLK
Bus Relinquish Time after Rising Edge of CS
NOTES
1Sample tested during initial release and after any redesign or process change
that may affect this parameter. All input signals are specified with tr = tf = 5 ns
(10% to 90%) and timed from a voltage level of 1.6 V.
2See timing diagrams below and Serial Interface section of this data sheet.
3Minimum time between read command and data read for all registers except
wavmode register, which is t9 = 500 ns min.
4Measured with the load circuit in Figure 1 and defined as the time required for
the output to cross 0.8 V or 2.4 V.
5Derived from the measured time taken by the data outputs to change 0.5 V
when loaded with the circuit in Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF
capacitor. The time quoted in the timing characteristics is the true bus relin-
quish time of the part and is independent of the bus loading.
TO
OUTPUT
PIN
CL
50pF
200A
1.6mA
IOL
IOH
2.1V
Figure 1. Load Circuit for Timing Specifications
CS
SCLK
DIN
CS
SCLK
DIN
DOUT
t1
1
t2 t3
t4 t5
0 A5 A4 A3 A2 A1 A0
t7
COMMAND BYTE
t7
DB7
DB0
MOST SIGNIFICANT BYTE
Figure 2. Serial Write Timing
t8
t6
DB7
DB0
LEAST SIGNIFICANT BYTE
t1
t9 t10
0 0 A5 A4 A3 A2 A1 A0
t11
DB7
t12
DB0
COMMAND BYTE
MOST SIGNIFICANT BYTE
Figure 3. Serial Read Timing
DB7
t13
DB0
LEAST SIGNIFICANT BYTE
–4– REV. 0
5 Page 
ADE7754
Figure 6 shows how the gain settings in PGA 1 (current channel)
and PGA 2 (voltage channel) are selected by various bits in the
gain register. The no-load threshold and sum of the absolute
value can also be selected in the gain register. See Table X.
GAIN REGISTER*
CURRENT AND VOLTAGE CHANNEL PGA CONTROL
76 5432 10
0 0 0 0 0 0 0 0 ADDR: 18h
RESERVED = 0 RESERVED = 0
ABS
PGA 2 GAIN SELECT
00 = ؋1
01 = ؋2
10 = ؋4
NO LOAD
PGA 1 GAIN SELECT
00 = ؋1
01 = ؋2
10 = ؋4
*REGISTER CONTENTS SHOW POWER-ON DEFAULTS
Figure 6. Analog Gain Register
ANALOG-TO-DIGITAL CONVERSION
The ADE7754 carries out analog-to-digital conversion using
second order Σ-∆ ADCs. The block diagram in Figure 7 shows a
first order (for simplicity) Σ-∆ ADC. The converter is made up of
two parts, the Σ-∆ modulator and the digital low-pass filter.
MCLK/12
ANALOG
LOW-PASS FILTER
RC
INTEGRATOR
+
LATCHED
COMPARATOR
– VREF
1 24
DIGITAL
LOW-PASS
....10100101......
FILTER
1-BIT DAC
Figure 7. First Order (⌺-⌬) ADC
A Σ-∆ modulator converts the input signal into a continuous
serial stream of 1s and 0s at a rate determined by the sampling
clock. In the ADE7754, the sampling clock is equal to CLKIN/12.
The 1-bit DAC in the feedback loop is driven by the serial data
stream. The DAC output is subtracted from the input signal.
If the loop gain is high enough, the average value of the DAC
output (and therefore the bit stream) will approach that of the
input signal level. For any given input value in a single sampling
interval, the data from the 1-bit ADC is virtually meaningless. Only
when a large number of samples are averaged will a meaningful
result be obtained. This averaging is carried out in the second part
of the ADC, the digital low-pass filter. Averaging a large number of
bits from the modulator, the low-pass filter can produce 24-bit
data-words that are proportional to the input signal level.
The Σ-∆ converter uses two techniques to achieve high resolu-
tion from what is essentially a 1-bit conversion technique. The
first is oversampling; the signal is sampled at a rate (frequency)
many times higher than the bandwidth of interest. For example,
the sampling rate in the ADE7754 is CLKIN/12 (833 kHz),
and the band of interest is 40 Hz to 2 kHz. Oversampling
spreads the quantization noise (noise due to sampling) over a
wider bandwidth. With the noise spread more thinly over a
wider bandwidth, the quantization noise in the band of interest
is lowered. See Figure 8.
Oversampling alone is not an efficient enough method to
improve the signal to noise ratio (SNR) in the band of interest.
For example, an oversampling ratio of 4 is required to increase
the SNR by only 6 dB (1 bit). To keep the oversampling ratio at
a reasonable level, the quantization noise can be shaped so that
most of the noise lies at the higher frequencies. In the Σ-∆
modulator, the noise is shaped by the integrator, which has a
high-pass type of response for the quantization noise. The result
is that most of the noise is at the higher frequencies, where it
can be removed by the digital low-pass filter. This noise shaping
is shown in Figure 8.
SIGNAL
ANTIALIAS FILTER (RC)
DIGITAL FILTER
SHAPED
NOISE
SAMPLING
FREQUENCY
NOISE
02
417
FREQUENCY (kHz)
833
SIGNAL
NOISE
HIGH RESOLUTION
OUTPUT FROM DIGITAL
LPF
02
417
FREQUENCY (kHz)
833
Figure 8. Noise Reduction Due to Oversampling
and Noise Shaping in the Analog Modulator
Antialias Filter
Figure 7 shows an analog low-pass filter (RC) on the input to
the modulator. This filter is used to prevent aliasing, an artifact
of all sampled systems. Frequency components in the input
signal to the ADC that are higher than half the sampling rate of
the ADC appear in the sampled signal at a frequency below half
the sampling rate. Figure 9 illustrates the effect; frequency com-
ponents (arrows shown in black) above half the sampling
frequency (also known as the Nyquist frequency), i.e., 417 kHz,
get imaged or folded back down below 417 kHz (arrows shown
in gray). This happens with all ADCs, regardless of the archi-
tecture. In the example shown, only frequencies near the sampling
frequency, i.e., 833 kHz, will move into the band of interest for
metering, i.e., 40 Hz to 2 kHz. This allows use of a very simple
LPF (low-pass filter) to attenuate these high frequencies (near
900 kHz) and thus prevent distortion in the band of interest. A
simple RC filter (single pole) with a corner frequency of 10 kHz
produces an attenuation of approximately 40 dBs at 833 kHz.
See Figure 9. This is sufficient to eliminate the effects of aliasing.
–10–
REV. 0
11 Page | ||
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