PDF ADE7759 Data sheet ( Hoja de datos )

Número de pieza	ADE7759
Descripción	Active Energy Metering IC with di/dt Sensor Interface
Fabricantes	Analog Devices
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No Preview Available ! a Active Energy Metering IC with di/dt Sensor Interface ADE7759* FEATURES High Accuracy, Supports IEC 687/1036 On-Chip Digital Integrator Allows Direct Interface with Current Sensors with di/dt Output Such as Rogowski Coil Less Than 0.1% Error over a Dynamic Range of 1000 to 1 On-Chip User-Programmable Threshold for Line Voltage SAG Detection and PSU Supervisory The ADE7759 Supplies Sampled Waveform Data and Active Energy (40 Bits) Digital Power, Phase and Input DC Offset Calibration On-Chip Temperature Sensor (Typical 1 LSB/؇C Resolution) SPI-Compatible Serial Interface Pulse Output with Programmable Frequency Interrupt Request Pin (IRQ) and IRQ Status Register Proprietary ADCs and DSP provide High Accuracy over Large Variations in Environmental Conditions and Time Reference 2.4 V ؎ 8% (20 ppm/؇C Typical) with External Overdrive Capability Single 5 V Supply, Low Power Consumption (25 mW Typical) GENERAL DESCRIPTION The ADE7759 is an accurate active power and energy measurement IC with a serial interface and a pulse output. The ADE7759 incor- porates two second order Σ-∆ ADCs, a digital integrator (on CH1), reference circuitry, temperature sensor, and all the signal processing required to perform active power and energy measurement. An on-chip digital integrator allows direct interface to di/dt current sensors such as a Rogowski coil. The digital integrator eliminates the need for an external analog integrator and pro- vides excellent long-term stability and precise phase matching between the current and the voltage channels. The integrator can be switched off if the ADE7759 is used with conventional current sensors. The ADE7759 contains a sampled Waveform register and an Active Energy register capable of holding at least 11.53 seconds of accumu- lated power at full ac load. Data is read from the ADE7759 via the serial interface. The ADE7759 also provides a pulse output (CF) with frequency that is proportional to the active power. In addition to active power information, the ADE7759 also provides various system calibration features, i.e., channel offset correction, phase calibration, and power offset correction. The part also incorporates a detection circuit for short duration voltage drop (SAG). The voltage threshold and the duration (in number of half-line cycles) of the drop are user programmable. An open drain logic output (SAG) goes active low when a sag event occurs. A zero crossing output (ZX) produces an output that is synchro- nized to the zero crossing point of the line voltage. This output can be used to extract timing or frequency information from the line. The signal is also used internally to the chip in the line cycle energy accumulation mode; i.e., the number of half-line cycles in which the energy accumulation occurs can be con- trolled. Line cycle energy accumulation enables a faster and more precise energy accumulation and is especially useful dur- ing calibration. This signal is also useful for synchronization of relay switching with a voltage zero crossing. The interrupt request output is an open drain, active low logic output. The Interrupt Status Register indicates the nature of the interrupt, and the Interrupt Enable Register controls which event produces an output on the IRQ pin. The ADE7759 is available in a 20-lead SSOP package. AVDD FUNCTIONAL BLOCK DIAGRAM RESET DVDD DGND MULTIPLIER INTEGRATOR MULTIPLIER ADE7759 ZX V1P ADC V1N dt LPF2 SAG HPF1 TEMP SENSOR APGAIN[11:0] PHCAL[7:0] APOS[15:0] V2P ADC ⌽ V2N DFC 2.4V 4k⍀ REFERENCE LPF1 REGISTERS AND SERIAL INTERFACE CFNUM[11:0] CFDEN[11:0] CF AGND REFIN/OUT DIN DOUT SCLK CS IRQ U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; others pending. REV. 0 CLKIN CLKOUT Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 1 page ADE7759 TIMING CHARACTERISTICS1, 2 (AVDD = DVDD = 5 V ؎ 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz XTAL, TMIN to TMAX = –40؇C to +85؇C unless otherwise noted.) Parameter A, B Versions Unit Test Conditions/Comments Write Timing t1 t2 t3 t4 t5 t6 t7 t8 Read Timing t9 t10 t113 t124 t134 20 150 150 10 5 6.4 4 100 4 4 30 100 10 100 10 ns (min) ns (min) ns (min) ns (min) ns (min) µs (min) µs (min) ns (min) CS Falling Edge to First SCLK Falling Edge SCLK Logic High Pulsewidth SCLK Logic Low Pulsewidth Valid Data Setup Time Before Falling Edge of SCLK Data Hold Time After SCLK Falling Edge Minimum Time between the End of Data Byte Transfers Minimum Time between Byte Transfers During a Serial Write CS Hold Time After SCLK Falling Edge µs (min) µs (min) ns (min) ns (max) ns (min) ns (max) ns (min) Minimum Time between Read Command (i.e., a Write to Communications Register) and Data Read Minimum Time between Data Byte Transfers During a Multibyte Read Data Access Time After SCLK Rising Edge following a Write to the Communi- cations Register Bus Relinquish Time After Falling Edge of SCLK Bus Relinquish Time After Rising Edge of CS NOTES 1Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to 90%) and timed from a voltage level of 1.6 V. 2See Figures 2 and 3 and Serial Interface section of this data sheet. 3Measured with the load circuit in Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V. 4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. REV. 0 CS SCLK t1 DIN CS SCLK t1 DIN DOUT 200␮A IOL TO OUTPUT PIN CL 50pF 2.1V 1.6mA IOH Figure 1. Load Circuit for Timing Specifications t8 t2 10 t3 t7 t4 t5 0 A4 A3 A2 A1 A0 DB7 t6 t7 DB0 DB7 DB0 COMMAND BYTE MOST SIGNIFICANT BYTE Figure 2. Serial Write Timing LEAST SIGNIFICANT BYTE t9 t10 t13 0 0 0 A4 A3 A2 A1 A0 t11 DB7 t11 DB0 DB7 t12 DB0 COMMAND BYTE MOST SIGNIFICANT BYTE Figure 3. Serial Read Timing LEAST SIGNIFICANT BYTE –5– 5 Page Test Circuits VDD I 10␮F 100nF 100nF 10␮F 1k⍀ 33nF RB 1k⍀ 33nF 110V 1k⍀ 33nF 600k⍀ 1k⍀ 33nF 10␮F 100nF CT TURN RATIO = 1800:1 CHANNEL 2 GAIN = 1 GAIN (CH1) RB 1 10⍀ 4 2.5⍀ AVDD DVDD RESET DIN V1P DOUT SCLK V1N U1 ADE7759 CS V2N CLKOUT CLKIN V2P REFIN/OUT IRQ SAG ZX CF AGND DGND TO SPI BUS (USED ONLY FOR CALIBRATION) Y1 3.58MHz 22pF 22pF NOT CONNECTED U3 TO FREQUENCY COUNTER PS2501-1 Test Circuit 1. Performance Curve (Integrator OFF) ADE7759 VDD I 10␮F 100nF 100nF 10␮F di/dt CURRENT SENSOR 100⍀ 1k⍀ 33nF 33nF 100⍀ 1k⍀ 33nF 33nF 110V 1k⍀ 33nF 600k⍀ 1k⍀ 33nF 10␮F 100nF CHANNEL 1 GAIN = 4 CHANNEL 2 GAIN = 1 AVDD DVDD RESET DIN V1P DOUT SCLK V1N U1 ADE7759 CS CLKOUT V2N CLKIN V2P REFIN/OUT IRQ SAG ZX CF AGND DGND TO SPI BUS (USED ONLY FOR CALIBRATION) Y1 3.58MHz 22pF 22pF NOT CONNECTED U3 TO FREQUENCY COUNTER PS2501-1 Test Circuit 2. Performance Curve (Integrator ON) ANALOG INPUTS The ADE7759 has two fully differential voltage input channels. The maximum differential input voltage for input pairs V1P/V1N and V2P/V2N are ± 0.5 V. In addition, the maximum signal level on analog inputs for V1P/V1N and V2P/V2N are ± 0.5 V with respect to AGND. Each analog input channel has a PGA (Programmable Gain Amplifier) with possible gain selections of 1, 2, 4, 8, and 16. The gain selections are made by writing to the Gain register— see Figure 5. Bits 0 to 2 select the gain for the PGA in Channel 1 and the gain selection for the PGA in Channel 2 is made via Bits 5 to 7. Figure 4 shows how a gain selection for Channel 1 is made using the Gain register. GAIN[7:0] GAIN (K) SELECTION V1P VIN V1N K ؋ VIN + OFFSET ADJUST (؎50mV) CH1OS[7:0] BIT 0 to 5: SIGN MAGNITUDE CODED OFFSET CORRECTION BIT 6: NOT USED BIT 7: DIGITAL INTEGRATOR (ON = 1, OFF = 0; DEFAULT ON) Figure 4. PGA in Channel 1 In addition to the PGA, Channel 1 also has a full-scale input range selection for the ADC. The ADC analog input range selection is also made using the Gain register—see Figure 2. As mentioned previously the maximum differential input voltage is 0.5 V. However, by using Bits 3 and 4 in the Gain register, the maximum ADC input voltage can be set to 0.5 V, 0.25 V, or 0.125 V. This is achieved by adjusting the ADC reference—see Reference Circuit section. Table I summarizes the maximum differential input signal level on Channel 1 for the various ADC range and gain selections. Table I. Maximum Input Signal Levels for Channel 1 Max Signal Channel 1 ADC Input Range Selection 0.5 V 0.25 V 0.125 V 0.5 V 0.25 V 0.125 V 0.0625 V 0.0313 V 0.0156 V 0.00781 V Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 GAIN REGISTER CHANNEL 1 AND CHANNEL 2 PGA CONTROL 76 54 32 10 00 00 00 0 0 ADDR: 0AH PGA 2 GAIN SELECT 000 = ؋1 001 = ؋2 010 = ؋4 011 = ؋8 100 = ؋16 *REGISTER CONTENTS SHOW POWER-ON DEFAULTS PGA 1 GAIN SELECT 000 = ؋1 001 = ؋2 010 = ؋4 011 = ؋8 100 = ؋16 CHANNEL 1 FULL SCALE SELECT 00 = 0.5V 01 = 0.25V 10 = 0.125V REV. 0 –11– Figure 5. Analog Gain Register 11 Page

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