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PDF ADF4153 Data sheet ( Hoja de datos )
| Número de pieza | ADF4153 | |
| Descripción | Fractional-N Frequency Synthesizer | |
| Fabricantes | Analog Devices | |
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Data Sheet
Fractional-N Frequency Synthesizer
ADF4153
FEATURES
GENERAL DESCRIPTION
RF bandwidth to 4 GHz
2.7 V to 3.3 V power supply
Separate VP allows extended tuning voltage
Y version available: −40°C to +125°C
Programmable fractional modulus
Programmable charge pump currents
3-wire serial interface
Analog and digital lock detect
Power-down mode
Pin-compatible with ADF4110/ADF4111/ADF4112/ADF4113
and ADF4106
Consistent RF output phase
Loop filter design possible with ADIsimPLL
Qualified for automotive applications
APPLICATIONS
CATV equipment
Base stations for mobile radio (GSM, PCS, DCS, WiMAX,
SuperCell 3G, CDMA, W-CDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, W-CDMA)
Wireless LANs, PMR
Communications test equipment
The ADF4153 is a fractional-N frequency synthesizer
that implements local oscillators in the upconversion
and downconversion sections of wireless receivers and
transmitters. It consists of a low noise digital phase
frequency detector (PFD), a precision charge pump, and
a programmable reference divider. There is a Σ-Δ based
fractional interpolator to allow programmable fractional-N
division. The INT, FRAC, and MOD registers define an
overall N divider (N = (INT + (FRAC/MOD))). In addition,
the 4-bit reference counter (R counter) allows selectable
REFIN frequencies at the PFD input. A complete phase-
locked loop (PLL) can be implemented if the synthesizer is
used with an external loop filter and a voltage controlled
oscillator (VCO).
A simple 3-wire interface controls all on-chip registers.
The device operates with a power supply ranging from
2.7 V to 3.3 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD VP SDVDD
RSET
ADF4153
REFIN
MUXOUT
×2
DOUBLER
4-BIT
R COUNTER
HIGH-Z
OUTPUT
MUX
VDD
DGND
VDD
RDIV
NDIV
LOCK
DETECT
THIRD ORDER
FRACTIONAL
INTERPOLATOR
REFERENCE
+ PHASE
FREQUENCY
– DETECTOR
CHARGE
PUMP
CP
CURRENT
SETTING
RFCP3 RFCP2 RFCP1
N-COUNTER
RFINA
RFINB
CLK
DATA
LE
24-BIT
DATA
REGISTER
FRACTION MODULUS
REG
REG
INTEGER
REG
AGND
DGND
Figure 1.
CPGND
Rev. F
Document Feedback
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADF4153
Data Sheet
SPECIFICATIONS
AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted;
dBm referred to 50 Ω.
Table 1.
Parameter
RF CHARACTERISTICS (3 V)
RF Input Frequency (RFIN)
REFERENCE CHARACTERISTICS
REFIN Input Frequency
REFIN Input Sensitivity
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency4
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
RSET Range
ICP Three-State Leakage Current
Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
DVDD, SDVDD
VP
IDD
Low Power Sleep Mode
B Version1
0.5/4.0
0.5/4.0
1.0/4.0
10/250
0.7/AVDD
10
±100
Y Version2
0.5/4.0
0.5/4.0
1.0/4.0
10/250
0.7/AVDD
10
±100
Unit
GHz min/max
GHz min/max
GHz min/max
MHz min/max
V p-p min/max
pF max
µA max
Test Conditions/Comments
See Figure 12 for input circuit
B Version: −8 dBm minimum/0 dBm maximum
Y Version: −6.5 dBm minimum/0 dBm maximum
For lower frequencies, ensure slew rate (SR) > 400 V/µs
−10 dBm/0 dBm minimum/maximum
See Figure 11 for input circuit
For f < 10 MHz, use a dc-coupled, CMOS-compatible
square wave; slew rate > 25 V/µs
Biased at AVDD/23
32 32 MHz max
5
312.5
2.5
1.5/10
1
2
2
2
5
312.5
2.5
1.5/10
4.5
2
2
2
mA typ
µA typ
% typ
kΩ min/max
nA typ
% typ
% typ
% typ
Programmable; see Table 9
With RSET = 5.1 kΩ
With RSET = 5.1 kΩ
Sink and source current
0.5 V < VCP < VP – 0.5
0.5 V < VCP < VP – 0.5
VCP = VP/2
1.4 1.4 V min
0.6 0.6 V max
±1 ±1 µA max
10 10 pF max
1.4 1.4 V min
0.4 0.4 V max
Open-drain 1 kΩ pull-up to 1.8 V
IOL = 500 µA
2.7/3.3
AVDD
AVDD/5.5
24
1
2.7/3.3
AVDD
AVDD/5.5
24
1
V min/V max
V min/V max
mA max
µA typ
20 mA typical
Rev. F | Page 4 of 24
5 Page 
ADF4153
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 14 is a simplified schematic of
the phase frequency detector. The PFD includes a fixed delay
element that sets the width of the antibacklash pulse, which is
typically 3 ns. This pulse ensures that there is no dead zone in the
PFD transfer function and gives a consistent reference spur level.
UP
HI D1 Q1
U1
+IN CLR1
DELAY
U3
CHARGE
PUMP
CP
CLR2 DOWN
HI D2 Q2
U2
–IN
Figure 14. PFD Simplified Schematic
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4153 allows the user to
access various internal points on the chip. The state of MUXOUT
is controlled by M3, M2, and M1 (see Table 8). Figure 15 shows
the MUXOUT section in block diagram form.
DVDD
THREE-STATE OUTPUT
LOGIC LOW
DIGITAL LOCK DETECT
R COUNTER DIVIDER
N COUNTER DIVIDER
ANALOG LOCK DETECT
LOGIC HIGH
MUX
CONTROL
MUXOUT
Figure 15. MUXOUT Schematic
DGND
s
Data Sheet
INPUT SHIFT REGISTERS
The ADF4153 digital section includes a 4-bit RF R counter,
a 9-bit RF N counter, a 12-bit FRAC counter, and a 12-bit
modulus counter. Data is clocked into the 24-bit shift register
on each rising edge of CLK. The data is clocked in MSB first.
Data is transferred from the shift register to one of four latches
on the rising edge of LE. The destination latch is determined by
the state of the two control bits (C2 and C1) in the shift register.
These are the 2 LSBs, DB1 and DB0, as shown in Figure 2. The
truth table for these bits is shown in Table 5. Table 6 shows a
summary of how the registers are programmed.
PROGRAM MODES
Table 5 through Table 10 show how to set up the program
modes in the ADF4153.
The ADF4153 programmable modulus is double buffered. This
means that two events have to occur before the part uses a new
modulus value. First, the new modulus value is latched into the
device by writing to the R divider register. Second, a new write
must be performed on the N divider register. Therefore, to
ensure that the modulus value is loaded correctly, the N divider
register must be written to any time that the modulus value is
updated.
Table 5. C2 and C1 Truth Table
Control Bits
C2 C1 Register
0 0 N Divider Register
0 1 R Divider Register
1 0 Control Register
1 1 Noise and Spur Register
Rev. F | Page 10 of 24
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet ADF4153.PDF ] | |
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