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PDF AT28BV256 Data sheet ( Hoja de datos )
| Número de pieza | AT28BV256 | |
| Descripción | 256K (32K x 8) Battery-Voltage Parallel EEPROMs | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Single 2.7V - 3.6V Supply
• Fast Read Access Time – 200 ns
• Automatic Page Write Operation
– Internal Address and Data Latches for 64 Bytes
– Internal Control Timer
• Fast Write Cycle Times
– Page Write Cycle Time: 10 ms Maximum
– 1- to 64-byte Page Write Operation
• Low Power Dissipation
– 15 mA Active Current
– 20 µA CMOS Standby Current
• Hardware and Software Data Protection
• Data Polling for End of Write Detection
• High Reliability CMOS Technology
– Endurance: 10,000 Cycles
– Data Retention: 10 Years
• JEDEC Approved Byte-wide Pinout
• Industrial Temperature Ranges
• Green (Pb/Halide-free) Packaging Option Only
256K (32K x 8)
Battery-Voltage
Parallel
EEPROMs
AT28BV256
1. Description
The AT28BV256 is a high-performance electrically erasable and programmable read-
only memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac-
tured with Atmel’s advanced nonvolatile CMOS technology, the device offers access
times to 200 ns with power dissipation of just 54 mW. When the device is deselected,
the CMOS standby current is less than 200 µA.
The AT28BV256 is accessed like a Static RAM for the read or write cycle without the
need for external components. The device contains a 64-byte page register to allow
writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to
64 bytes of data are internally latched, freeing the address and data bus for other
operations. Following the initiation of a write cycle, the device will automatically write
the latched data using an internal control timer. The end of a write cycle can be
detected by Data polling of I/O7. Once the end of a write cycle has been detected a
new access for a read or write can begin.
Atmel’s AT28BV256 has additional features to ensure high quality and manufactura-
bility. The device utilizes internal error correction for extended endurance and
improved data retention characteristics. An optional software data protection mecha-
nism is available to guard against inadvertent writes. The device also includes an
extra 64 bytes of EEPROM for device identification or tracking.
0273K–PEEPR–2/09
1 page  
AT28BV256
5.6.1
Hardware Protection
Hardware features protect against inadvertent writes to the AT28BV256 in the following ways:
(a) VCC power-on delay – once VCC has reached 1.8V (typical) the device will automatically time
out 10 ms (typical) before allowing a write; (b) write inhibit – holding any one of OE low, CE high
or WE high inhibits write cycles; and (c) noise filter – pulses of less than 15 ns (typical) on the
WE or CE inputs will not initiate a write cycle.
5.6.2
Software Data Protection
A software-controlled data protection feature has been implemented on the AT28BV256. Soft-
ware data protection (SDP) helps prevent inadvertent writes from corrupting the data in the
device. SDP can prevent inadvertent writes during power-up and power-down as well as any
other potential periods of system instability.
The AT28BV256 can only be written using the software data protection feature. A series of three
write commands to specific addresses with specific data must be presented to the device before
writing in the byte or page mode. The same three write commands must begin each write opera-
tion. All software write commands must obey the page mode write timing specifications. The
data in the 3-byte command sequence is not written to the device; the address in the command
sequence can be utilized just like any other location in the device.
Any attempt to write to the device without the 3-byte sequence will start the internal write timers.
No data will be written to the device; however, for the duration of tWC, read operations will effec-
tively be polling operations.
5.7 Device Identification
An extra 64 bytes of EEPROM memory are available to the user for device identification. By rais-
ing A9 to 12V ± 0.5V and using address locations 7FC0H to 7FFFH the additional bytes may be
written to or read from in the same manner as the regular memory array.
0273K–PEEPR–2/09
5
5 Page 
19. Data Polling Characteristics(1)
Symbol Parameter
tDH
tOEH
tOE
tWR
Notes:
Data Hold Time
OE Hold Time
OE to Output Delay(2)
Write Recovery Time
1. These parameters are characterized and not 100% tested.
2. See “AC Read Characteristics” on page 7.
20. Data Polling Waveforms
AT28BV256
Min Typ Max Units
0 ns
0 ns
ns
0 ns
tOEH
tDH tOE
tWR
21. Toggle Bit Characteristics(1)
Symbol Parameter
tDH
tOEH
tOE
tOEHP
tWR
Notes:
Data Hold Time
OE Hold Time
OE to Output Delay(2)
OE High Pulse
Write Recovery Time
1. These parameters are characterized and not 100% tested.
2. See “AC Read Characteristics” on page 7.
22. Toggle Bit Waveforms
Min Typ Max Units
10 ns
10 ns
ns
150 ns
0 ns
tOEH
tDH tOE
Notes:
1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
0273K–PEEPR–2/09
tWR
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet AT28BV256.PDF ] | |
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