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PDF AT28C040 Data sheet ( Hoja de datos )
| Número de pieza | AT28C040 | |
| Descripción | 4-Megabit (512K x 8) Paged Parallel EEPROM | |
| Fabricantes | ATMEL Corporation | |
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Features
• Read Access Time – 200 ns
• Automatic Page Write Operation
– Internal Address and Data Latches for 256 Bytes
– Internal Control Timer
• Fast Write Cycle Time
– Page Write Cycle Time – 10 ms Maximum
– 1 to 256 Byte Page Write Operation
• Low Power Dissipation
– 50 mA Active Current
• Hardware and Software Data Protection
• DATA Polling for End of Write Detection
• High Reliability CMOS Technology
– Endurance: 10,000 Cycles
– Data Retention: 10 Years
• Single 5V ± 10% Supply
• CMOS and TTL Compatible Inputs and Outputs
• JEDEC Approved Byte-Wide Pinout
1. Description
The AT28C040 is a high-performance electrically erasable and programmable read-
only memory (EEPROM). Its 4 megabits of memory is organized as 524,288 words by
8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device
offers access times to 200 ns with power dissipation of just 440 mW.
The AT28C040 is accessed like a static RAM for the read or write cycle without the
need for external components. The device contains a 256-byte page register to allow
writing of up to 256 bytes simultaneously. During a write cycle, the address and 1 to
256 bytes of data are internally latched, freeing the address and data bus for other
operations. Following the initiation of a write cycle, the device will automatically write
the latched data using an internal control timer. The end of a write cycle can be
detected by Data Polling of I/O7. Once the end of a write cycle has been detected, a
new access for a read or write can begin.
Atmel's AT28C040 has additional features to ensure high quality and manufacturabil-
ity. The device utilizes internal error correction for extended endurance and improved
data retention characteristics. An optional software data protection mechanism is
available to guard against inadvertent writes. The device also includes an extra 256
bytes of EEPROM for device identification or tracking.
4-Megabit
(512K x 8)
Paged Parallel
EEPROMs
AT28C040
0542F–PEEPR–2/09
1 page  
AT28C040
5.6.1
Hardware Protection
Hardware features protect against inadvertent writes to the AT28C040 in the following ways:
(a) VCC sense – if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power-on
delay – once VCC has reached 3.8V the device will automatically time out 5 ms (typical) before
allowing a write: (c) write inhibit – holding any one of OE low, CE high or WE high inhibits write
cycles; (d) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate
a write cycle.
5.6.2
Software Data Protection
A software controlled data protection feature has been implemented on the AT28C040. When
enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP
feature may be enabled or disabled by the user; the AT28C040 is shipped from Atmel with SDP
disabled.
SDP is enabled when the host system issues a series of three write commands; three specific
bytes of data are written to three specific addresses (refer to Software Data Protection Algo-
rithm). After writing the 3-byte command sequence and after tWC, the entire AT28C040 will be
protected against inadvertent write operations. It should be noted that once protected, the host
can still perform a byte or page write to the AT28C040. To do so, the same 3-byte command
sequence used to enable SDP must precede the data to be written.
Once set, SDP will remain active unless the disable command sequence is issued. Power transi-
tions do not disable SDP, and SDP will protect the AT28C040 during power-up and power-down
conditions. All command sequences must conform to the page write timing specifications. The
data in the enable and disable command sequences is not written to the device, and the
memory addresses used in the sequence may be written with data in either a byte or page write
operation.
After setting SDP, any attempt to write to the device without the 3-byte command sequence will
start the internal write timers. No data will be written to the device; however, for the duration of
tWC, read operations will effectively be polling operations.
5.7 Device Identification
An extra 256 bytes of EEPROM memory are available to the user for device identification. By
raising A9 to 12V ± 0.5V and using address locations 7FF80H to 7FFFFH, the bytes may be writ-
ten to or read from in the same manner as the regular memory array.
5.8 Optional Chip Erase Mode
The entire device can be erased using a 6-byte software erase code. Please see Software Chip
Erase application note for details.
0542F–PEEPR–2/09
5
5 Page 
21. Data Polling Characteristics(1)
Symbol Parameter
tDH
tOEH
tOE
tWR
Notes:
Data Hold Time
OE Hold Time
OE to Output Delay(2)
Write Recovery Time
1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
22. Data Polling Waveforms
AT28C040
Min Typ Max Units
10 ns
10 ns
ns
0 ns
23. Toggle Bit Characteristics(1)
Symbol Parameter
tDH
tOEH
tOE
tOEHP
tWR
Notes:
Data Hold Time
OE Hold Time
OE to Output Delay(2)
OE High Pulse
Write Recovery Time
1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
24. Toggle Bit Waveforms(1)(2)(3)
Min Typ Max Units
10 ns
10 ns
ns
150 ns
0 ns
Notes:
1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
0542F–PEEPR–2/09
11
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| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet AT28C040.PDF ] | |
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