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PDF AT29C257 Data sheet ( Hoja de datos )
| Número de pieza | AT29C257 | |
| Descripción | 256K 32K x 8 5-volt Only CMOS Flash Memory | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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AT29C257
Features
Fast Read Access Time - 70 ns
• 5-Volt-Only Reprogramming
•• Page Program Operation
Single Cycle Reprogram (Erase and Program)
Internal Address and Data Latches for 64-Bytes
Internal Program Control and Timer
• Hardware and Software Data Protection
•• Fast Program Cycle Times
Page (64-Byte) Program Time - 10 ms
Chip Erase Time - 10 ms
DATA Polling for End of Program Detection
•• Low Power Dissipation
50 mA Active Current
300 µA CMOS Standby Current
Typical Endurance > 10,000 Cycles
•• Single 5V ± 10% Supply
CMOS and TTL Compatible Inputs and Outputs
•• Pin-Compatible with AT29C010A and AT29C512 for Easy System Upgrades
256K (32K x 8)
5-volt Only
CMOS Flash
Memory
Description
The AT29C257 is a 5-volt-only in-system Flash programmable and erasable read only
memory (PEROM). Its 256K of memory is organized as 32,768 words by 8 bits. Manu-
factured with Atmel’s advanced nonvolatile CMOS technology, the device offers ac-
cess times to 70 ns with power dissipation of just 275 mW. When the device is dese-
lected, the CMOS standby current is less than 300 µA. The device endurance is such
that any sector can typically be written to in excess of 10,000 times.
To allow for simple in-system reprogrammability, the AT29C257 does not require high
input voltages for programming. Five-volt-only commands determine the operation of
the device. Reading data out of the device is similar to reading from a static RAM.
Reprogramming the AT29C257 is performed on a page basis; 64-bytes of data are
loaded into the device and then simultaneously programmed. The contents of the
entire device may be erased by using a 6-byte software code (although erasure before
programming is not needed).
During a reprogram cycle, the address locations and 64-bytes of data are internally
latched, freeing the address and data bus for other operations. Following the initiation
of a program cycle, the device will automatically erase the page and then program the
latched data using an internal control timer. The end of a program cycle can be de-
tected by DATA polling of I/O7. Once the end of a program cycle has been detected
a new access for a read, program or chip erase can begin.
AT29C257
Pin Configurations
Pin Name Function
A0 - A14 Addresses
CE Chip Enable
OE Output Enable
WE Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
DC Don’t Connect
PLCC Top View
0012K
4-105
1 page  
AT29C257
AC Read Characteristics
Symbol
tACC
tCE (1)
tOE (2)
tDF (3, 4)
tOH
Parameter
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
Output Hold from OE, CE
or Address, whichever
occurred first
AT29C257-70 AT29C257-90 AT29C257-12 AT29C257-15
Min Max Min Max Min Max Min Max
70 90 120 150
70 90 120 150
0 40 0 40 0 50 0 70
0 25 0 25 0 30 0 40
0000
Units
ns
ns
ns
ns
ns
AC Read Waveforms (1, 2, 3, 4)
Notes: 1. CE may be delayed up to tACC - tCE after the address
transition without impact on tACC .
2. OE may be delayed up to tCE - tOE after the falling
edge of CE without impact on tCE or by tACC - tOE
after an address change without impact on tACC .
3. tDF is specified from OE or CE whichever occurs first
(CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance (f = 1 MHz, T = 25°C) (1)
Typ Max
CIN 4 6
COUT
8 12
Note: 1. This parameter is characterized and is not 100% tested.
Units
pF
pF
Conditions
VIN = 0V
VOUT = 0V
4-109
5 Page 
AT29C257
4-115
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AT29C257.PDF ] | |
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