|
|
PDF 100310QC Data sheet ( Hoja de datos )
| Número de pieza | 100310QC | |
| Descripción | Low Skew 2:8 Differential Clock Driver | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 100310QC (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
|
No Preview Available !
October 1991
Revised November 1999
100310
Low Skew 2:8 Differential Clock Driver
General Description
The 100310 is a low skew 8-bit differential clock driver
which is designed to select between two separate differen-
tial clock inputs. The low output to output skew (< 50 ps) is
maintained for either clock input. A LOW on the select pin
(SEL) selects CLKINA, CLKINA and a HIGH on the SEL
pin selects the CLKINB, CLKINB inputs.
The 100310 is ideal for those applications that need the
ability to freely select between two clocks, or to maintain
the ability to switch to an alternate or backup clock should a
problem arise with the primary clock source.
A VBB output is provided for single-ended operation.
Features
s Low output to output skew
s Differential inputs and outputs
s Allows multiplexing between two clock inputs
s Voltage compensated operating range: −4.2V to −5.7V
s Available to industrial grade temperature range
(PLCC package only)
Ordering Code:
Order Number Package Number
Package Description
100310QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100310QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
28-Pin PLCC
Pin Descriptions
Pin Names
CLKINn, CLKINn
SEL
CLK0–7, CLK0–8
VBB
NC
Description
Differential Clock Inputs
Select
Differential Clock Outputs
VBB Output
No Connect
Truth Table
CLKINA CLKINA CLKINB CLKINB SEL CLKn CLKn
H L X X LH L
L H X X LL H
X X H L HH L
X X L H HL H
© 1999 Fairchild Semiconductor Corporation DS010943
www.fairchildsemi.com
1 page  
Test Circuit
Note:
Shown for testing CLKIN to CLK1 in the differential mode.
L1, L2, L3 and L4 = equal length 50Ω impedance lines.
All unused inputs and outputs are loaded with 50Ω in parallel with ≤3 pF to GND.
Scope should have 50Ω input terminator internally.
FIGURE 1. AC Test Circuit
Switching Waveforms
FIGURE 2. Propagation Delay, SEL to Outputs
FIGURE 3. Propagation Delay, CLKIN/CLKIN to Outputs
FIGURE 4. Transition Times
5
www.fairchildsemi.com
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet 100310QC.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 100310QC | Low Skew 2:8 Differential Clock Driver | Fairchild Semiconductor |
| 100310QI | Low Skew 2:8 Differential Clock Driver | Fairchild Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |