DataSheetWiki


M2085 fiches techniques PDF

Integrated Circuit Solution Inc - VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN

Numéro de référence M2085
Description VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN
Fabricant Integrated Circuit Solution Inc 
Logo Integrated Circuit Solution Inc 





1 Page

No Preview Available !





M2085 fiche technique
Integrated
Circuit
Systems, Inc.
P r e l i m i n a r y I n f o r m a t i o n M2080/81/82
M2085/86/87
VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN
GENERAL DESCRIPTION
PIN ASSIGNMENT (9 x 9 mm SMT)
The M2080/81/82 and M2085/86/87 are VCSO (Voltage
Controlled SAW Oscillator) based
clock PLLs designed for FEC clock
ratio translation in 10Gb optical
systems such as OC-192 or 10GbE.
They support FEC (Forward Error
Correction) clock multiplication
ratios, both forward (mapping) and
inverse (de-mapping). Multiplication ratios are
pin-selected from pre-programming look-up tables.
FEATURES
Integrated SAW delay line; Output of 15 to 700 MHz *
Low phase jitter < 0.5 ps rms typical
(12kHz to 20MHz or 50kHz to 80MHz)
LVPECL clock output (CML and LVDS options available)
Pin-selectable PLL divider ratios support FEC ratios
• M2080/85: OTU1 (255/238) and OTU2 (255/237) Mapping
• M2081/86: OTU1 (238/255) or OTU2 (237/255) De-mapping
• M2082/87: OTU1 (238/255) and OTU2 (237/255) De-mapping
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
Loss of Lock (LOL) output pin; Narrow Bandwidth
control input (NBW pin)
AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure
Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
Options for Hitless Switching (HS) with or without
Phase Build-out (PBO) to enable SONET (GR-253) /SDH
(G.813) MTIE and TDEV compliance during reselection
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
FIN_SEL0
FEC_SEL0
FEC_SEL1
LOL
NBW
VCC
DNC
DNC
DNC
28 18
29 17
30 M 2 0 8 0
31
32 S e r i e s
16
15
14
33 13
34 ( T o p V i e w ) 12
35 11
36 10
P_SEL0
P_SEL1
nFOUT
FOUT
GND
REF_ACK
AUTO
VCC
GND
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using M2081-11-622.0800 FEC De-Map Ratios
FEC De-Map
PLL Ratio
Mfec / Rfec
Base Input Rate 1
(MHz)
Output Clock
(either output)
MHz
1/1
237/255
238/255
622.0800
666.5143
669.3266
622.08
or
155.52
Table 1: Example I/O Clock Frequency Combinations
Note 1: Input reference clock can be the base frequency shown
divided by “Mfin” (as shown in Tables 3 and 4 on pg. 3).
* Specify VCSO center frequency at time of order.
SIMPLIFIED BLOCK DIAGRAM
NBW
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
M2080 Series
MUX
0 Rfec
Div
1
PLL
Phase
Detector
0
1
Auto
Ref Sel
LOL Phase
Detector
Mfec Div
2
FEC_SEL1:0
2
FIN_SEL1:0
3
P_SEL2:0
Mfec / Rfec Divider
LUT
Mfin Divider
LUT
Loop Filter
Mfin Divider
(1, 4, 8, 32 or
1, 4, 8, 16)
VCSO
P Divider
(1, 4, 8, 32 or TriState)
Tri-state
P Divider
LUT
Figure 2: Simplified Block Diagram
LOL
FOUT
nFOUT
M2080/81/82 M2085/86/87 Datasheet Rev 0.4
Revised 30Jul2004
M2080/81/82 VCSO FEC PLL with AutoSwitch for SONET/OTN
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400

PagesPages 14
Télécharger [ M2085 ]


Fiche technique recommandé

No Description détaillée Fabricant
M208 Single Chip Organ STMicroelectronics
STMicroelectronics
M208-A4 Contact Image Sensor Module CMOS Sensor
CMOS Sensor
M208-A6 Contact Image Sensor Module CMOS Sensor
CMOS Sensor
M208-A8 Contact Image Sensor Module CMOS Sensor
CMOS Sensor

US18650VTC5A

Lithium-Ion Battery

Sony
Sony
TSPC106

PCI Bus Bridge Memory Controller

ATMEL
ATMEL
TP9380

NPN SILICON RF POWER TRANSISTOR

Advanced Semiconductor
Advanced Semiconductor


www.DataSheetWiki.com    |   2020   |   Contactez-nous  |   Recherche