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PDF FDC37B78X Data sheet ( Hoja de datos )
| Número de pieza | FDC37B78X | |
| Descripción | Super I/O Controller | |
| Fabricantes | SMSC Corporation | |
| Logotipo |  |
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FDC37B78x
Super I/O Controller with ACPI Support,
Real Time Clock and Consumer IR
FEATURES
5 Volt Operation
PC98/99 and ACPI 1.0 Compliant
Battery Back-up for Wake-Events
ISA Plug-and-Play Compatible Register Set
- 12 IRQ Options
- 15 Serial IRQ Options
- 16 Bit Address Qualification
- Four DMA Options
- 12mA AT Bus Drivers
BIOS Buffer
20 GPI/O Pins
32KHz Standby Clock Output
Soft Power Management
ACPI/PME Support
SCI/SMI Support
- Watchdog timer
- Power Button Override Event
- Either Edge Triggered Interrupts
Intelligent Auto Power Management
- Shadowed Write-only Registers
- Programmable Wake-up Event Interface
8042 Keyboard Controller
- 2K Program ROM
- 256 Bytes Data RAM
- Asynchronous Access to Two Data
Registers and One Status Register
- Supports Interrupt and Polling Access
- 8 Bit Timer/Counter
- Port 92 Support
- Fast Gate A20 and Hardware Keyboard
Reset
Real Time Clock
- Day of Month Alarm, Century Byte
- MC146818 and DS1287 Compatible
- 256 Bytes of Battery Backed CMOS in
Two Banks of 128 Bytes
- 128 Bytes of CMOS RAM Lockable in
4x32 Byte Blocks
- 12 and 24 Hour Time Format
- Binary and BCD Format
- 5μA Standby Battery Current (max)1
2.88MB Super I/O Floppy Disk Controller
- Relocatable to 480 Different Addresses
- Licensed CMOS 765B Floppy Disk
Controller
- Advanced Digital Data Separator
- SMSC's Proprietary 82077AA
Compatible Core
- Sophisticated Power Control Circuitry
(PCC) Including Multiple Powerdown
Modes for Reduced Power
Consumption
- Supports Two Floppy Drives Directly
- Software Write Protect
- FDC on Parallel Port
- Low Power CMOS Design
- Supports Vertical Recording Format
- 16 Byte Data FIFO
- 100% IBM Compatibility
- Detects All Overrun and Underrun
Conditions
- 24mA Drivers and Schmitt Trigger
Inputs
Enhanced FDC Digital Data Separator
- Low Cost Implementation
- No Filter Components Required
- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps,
250 Kbps Data Rates
- Programmable Precompensation
Modes
1
1 page  
AC TIMING DIAGRAMS .............................................................................................................. 223
CAPACITIVE LOADING ......................................................................................................... 223
IOW Timing Port 92 ................................................................................................................ 224
POWER-UP TIMING................................................................................................................ 225
Button Timing.......................................................................................................................... 226
ROM INTERFACE.................................................................................................................... 227
ISA WRITE ................................................................................................................................ 228
ISA READ.................................................................................................................................. 229
8042 CPU .................................................................................................................................. 231
CLOCK TIMING........................................................................................................................ 232
Burst Transfer DMA Timing ................................................................................................. 235
DISK DRIVE TIMING ............................................................................................................... 237
SERIAL PORT .......................................................................................................................... 238
Parallel Port.............................................................................................................................. 239
EPP 1.9 Data or Address Write Cycle................................................................................ 240
EPP 1.9 Data or Address Read Cycle................................................................................ 242
EPP 1.7 Data Or Address Write Cycle ............................................................................... 244
EPP 1.7 Data or Address Read Cycle................................................................................ 246
ECP PARALLEL PORT TIMING ........................................................................................... 249
Serial Port Infrared Timing................................................................................................... 254
5
5 Page 
PIN
No./QFP
NAME
TOTAL SYMBOL
127 Clear to Send 2
1 nCTS2
128 Data Terminal Ready
1 nDTR2
125 Data Set Ready 2
1 nDSR2
122 Data Carrier Detect 2
1 nDCD2
120 Ring Indicator 2
1 nRI2
PARALLEL PORT INTERFACE (17)
96-103 Parallel Port Data Bus
8 PD[0:7]
95 Printer Select
1 nSLCTIN
94 Initiate Output
1 nINIT
110 Auto Line Feed
1 nALF
111 Strobe Signal
1 nSTROBE
107 Busy Signal
1 BUSY
108 Acknowledge Handshake
1 nACK
106 Paper End
1 PE
105 Printer Selected
1 SLCT
109 Error at Printer
1 nERROR
KEYBOARD/MOUSE INTERFACE (6)
70 Keyboard Data
1 KDAT
71 Keyboard Clock
1 KCLK
72 Mouse Data
1 MDAT
73 Mouse Clock
1 MCLK
75 Keyboard Reset
1 KBDRST
(Note 2)
76 Gate A20
1 A20M
Note 1 The “n” as the first letter of a signal name indicates an “Active Low” signal.
Note 2 KBDRST is active low.
Note 3 This pin defaults to an output and low.
BUFFER TYPE
I
O4
I
I
I
IOP14
OP14
OP14
OP14
OP14
I
I
I
I
I
IOD16
IOD16
IOD16
IOD16
O4
O4
10
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet FDC37B78X.PDF ] | |
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