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Numéro de référence | FDC6321C | ||
Description | Dual N & P Channel / Digital FET | ||
Fabricant | Fairchild Semiconductor | ||
Logo | |||
1 Page
April 1999
FDC6321C
Dual N & P Channel , Digital FET
General Description
These dual N & P Channel logic level enhancement mode
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. This device has been designed
especially for low voltage applications as a replacement for
digital transistors in load switching applications. Since bias
resistors are not required this dual digital FET can replace
several digital transistors with different bias resistors.
Features
N-Ch 25 V, 0.68 A, RDS(ON) = 0.45 Ω @ VGS= 4.5 V
P-Ch -25 V, -0.46 A, RDS(ON) = 1.1 Ω @ VGS= -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3 V circuits. VGS(th) < 1.0V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Replace multiple dual NPN & PNP digital transistors.
SOT-23
SuperSOTTM-6
Mark:.321
D2
S1
D1
SuperSOTTM-8
SuperSOT TM-6
G2
S2
G1
SO-8
SOT-223
SOIC-16
43
52
61
Absolute Maximum Ratings TA = 25oC unless other wise noted
Symbol Parameter
N-Channel
VDSS, VCC
VGSS, VIN
ID, IO
Drain-Source Voltage, Power Supply Voltage
Gate-Source Voltage,
Drain/Output Current - Continuous
- Pulsed
25
8
0.68
2
PD Maximum Power Dissipation
(Note 1a)
(Note 1b)
TJ,TSTG
ESD
Operating and Storage Tempature Ranger
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a)
RθJC Thermal Resistance, Junction-to-Case (Note 1)
0.9
0.7
-55 to 150
6
140
60
P-Channel
-25
-8
-0.46
-1.5
© 1999 Fairchild Semiconductor Corporation
Units
V
V
A
W
°C
kV
°C/W
°C/W
FDC6321C.RevB
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Pages | Pages 11 | ||
Télécharger | [ FDC6321C ] |
No | Description détaillée | Fabricant |
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