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PDF FDC636P Data sheet ( Hoja de datos )
| Número de pieza | FDC636P | |
| Descripción | P-Channel Logic Level Enhancement Mode Field Effect Transistor | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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May 1998
FDC636P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These P-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. These devices are particularly suited
for low voltage applications such as cellular phone and
notebook computer power management and other battery
powered circuits where high-side switching, and low in-line
power loss are needed in a very small outline surface
mount package.
Features
-2.8 A, -20 V. RDS(ON) = 0.130 Ω @ VGS = -4.5 V
RDS(ON) = 0.180 Ω @ VGS = -2.5 V.
SuperSOTTM-6 package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
SOT-23
SuperSOTTM-6
SuperSOTTM-8
S
D
D .636
G
D
SuperSOT TM -6 pin 1 D
SO-8
SOT-223
SOIC-16
16
25
34
Absolute Maximum RatingsTA = 25°C unless otherwise noted
Symbol Parameter
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage
ID Drain Current - Continuous
- Pulsed
(Note 1a)
PD Maximum Power Dissipation
(Note 1a)
(Note 1b)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA
RθJC
Thermal Resistance, Junction-to-Ambient (Note 1a)
Thermal Resistance, Junction-to-Case
(Note 1)
© 1998 Fairchild Semiconductor Corporation
FDC636P
-20
±8
-2.8
-11
1.6
0.8
-55 to 150
78
30
Units
V
V
A
W
°C
°C/W
°C/W
FDC636P Rev.B
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet FDC636P.PDF ] | |
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