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Número de pieza | FDS2572 | |
Descripción | 150V/ 0.047 Ohms/ 4.9A/ N-Channel UltraFET Trench MOSFET | |
Fabricantes | Fairchild Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de FDS2572 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
No Preview Available ! October 2001
FDS2572
150V, 0.047 Ohms, 4.9A, N-Channel UltraFET® Trench MOSFET
General Description
UltraFET® devices combine characteristics that enable
benchmark efficiency in power conversion applications.
Optimized for Rds(on), low ESR, low total and Miller gate
charge, these devices are ideal for high frequency DC to
DC converters.
Applications
• DC/DC converters
• Telecom and Data-Com Distributed Power Architectures
• 48-volt I/P Half-Bridge/Full-Bridge
• 24-volt Forward and Push-Pull topologies
Features
• RDS(ON) = 0.040Ω (Typ.), VGS = 10V
• Qg(TOT) = 29nC (Typ.), VGS = 10V
• Low QRR Body Diode
• Maximized efficiency at high frequencies
• UIS Rated
DD
DD
DD
DD
5
6
SO-8
Pin 1 SO-8 SS SS SS GG
MOSFET Maximum Ratings TA=25°C unless otherwise noted
Symbol
VDSS
VGS
ID
PD
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
Continuous (TC = 25oC, VGS = 10V, RθJA = 50 oC/W)
Continuous (TC = 100oC, VGS = 10V, RθJA = 50 oC/W)
Pulsed
Power dissipation
Derate above 25oC
TJ, TSTG
Operating and Storage Temperature
7
8
Ratings
150
±20
4.9
3.1
Figure 4
2.5
20
-55 to 150
Thermal Characteristics
RθJC
RθJA
RθJA
Thermal Resistance Junction to Case
Thermal Resistance Junction to Case at 10 seconds
Thermal Resistance Junction to Case at steady state
(NOTE1)
(NOTE2)
(NOTE2)
25
50
85
Package Marking and Ordering Information
Device Marking
FDS2572
Device
FDS2572
Reel Size
330mm
Tape Width
12mm
4
3
2
1
Units
V
V
A
A
A
W
mW/oC
oC
oC/W
oC/W
oC/W
Quantity
2500units
©2001 Fairchild Semiconductor Corporation
FDS2572 Rev. B, October 2001
1 page Typical Characteristic (Continued)
5000
1000
CRSS = CGD
100
CISS = CGS + CGD
COSS ≅ CDS + CGD
VGS = 0V, f = 1MHz
10
0.1 1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
150
Figure 11. Capacitance vs Drain to Source
Voltage
10
VDD = 75V
8
6
4
2
0
0
WAVEFORMS IN
DESCENDING ORDER:
ID = 4.9A
ID = 1A
5 10 15 20 25 30 35
Qg, GATE CHARGE (nC)
Figure 12. Gate Charge Waveforms for Constant
Gate Currents
Test Circuits and Waveforms
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
tP
0V
RG
VDS
L
DUT
+
VDD
-
IAS
0.01Ω
0
tP
IAS
BVDSS
VDS
VDD
tAV
Figure 13. Unclamped Energy Test Circuit
VDS D1
VGS
Ig(REF)
L
DUT
+
VDD
-
Figure 15. Gate Charge Test Circuit
Figure 14. Unclamped Energy Waveforms
VDD
Qg(TOT)
VDS
VGS = 10V
VGS
VGS = 2V
0
Qg(TH)
Qgs2
Qgs
Qgd
Ig(REF)
0
Figure 16. Gate Charge Waveforms
©2001 Fairchild Semiconductor Corporation
FDS2572 Rev. B, October 2001
5 Page MS-012AA
8 LEAD JEDEC MS-012AA SMALL OUTLINE PLASTIC PACKAGE
E
E1
D
h x 45o
L
0.060
1.52
A
A1
e
b
c
0o- 8o
0.004 IN
0.10 mm
0.050
1.27
0.155
4.0
0.275
7.0
0.024
0.6
MINIMUM RECOMMENDED FOOTPRINT FOR
SURFACE-MOUNTED APPLICATIONS
MS-012AA
12mm TAPE AND REEL
1.5mm
DIA. HOLE
12mm
SYMBOL
INCHES
MIN MAX
MILLIMETERS
MIN MAX
NOTES
A 0.0532 0.0688 1.35 1.75
-
A1 0.004 0.0098 0.10 0.25
b 0.013 0.020 0.33 0.51
-
-
c 0.0075 0.0098 0.19 0.25
-
D 0.189 0.1968 4.80 5.00 2
E 0.2284 0.244 5.80 6.20
-
E1 0.1497 0.1574 3.80 4.00
e 0.050 BSC 1.27 BSC
3
-
H 0.0099 0.0196 0.25 0.50
-
L 0.016 0.050 0.40 1.27 4
NOTES:
1. All dimensions are within allowable dimensions of
Rev. C of JEDEC MS-012AA outline dated 5-90.
2. Dimension “D” does not include mold flash, protru-
sions or gate burrs. Mold flash, protrusions or gate
burrs shall not exceed 0.006 inches (0.15mm) per
side.
3. Dimension “E1” does not include inter-lead flash or
protrusions. Inter-lead flash and protrusions shall
not exceed 0.010 inches (0.25mm) per side.
4. “L” is the length of terminal for soldering.
5. The chamfer on the body is optional. If it is not
present, a visual index feature must be located with-
in the crosshatched area.
6. Controlling dimension: Millimeter.
7. Revision 8 dated 5-99.
4.0mm
USER DIRECTION OF FEED
2.0mm
1.75mm
CL
COVER TAPE
8.0mm
GENERAL INFORMATION
1. 2500 PIECES PER REEL.
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
3. MEETS EIA-481 REVISION “A” SPECIFICATIONS.
40mm MIN.
ACCESS HOLE
18.4mm
330mm
13mm
50mm
12.4mm
©2001 Fairchild Semiconductor Corporation
FDS2572 Rev. B, October 2001
11 Page |
Páginas | Total 12 Páginas | |
PDF Descargar | [ Datasheet FDS2572.PDF ] |
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