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PDF FDS3912 Data sheet ( Hoja de datos )
| Número de pieza | FDS3912 | |
| Descripción | 100V Dual N-Channel PowerTrench MOSFET | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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October 2001
FDS3912
100V Dual N-Channel PowerTrench® MOSFET
General Description
These N-Channel MOSFETs have been designed
specifically to improve the overall efficiency of DC/DC
converters using either synchronous or conventional
switching PWM controllers.
These MOSFETs feature faster switching and lower
gate charge than other MOSFETs with comparable
RDS(ON) specifications. The result is a MOSFET that is
easy and safer to drive (even at very high frequencies),
and DC/DC power supply designs with higher overall
efficiency.
Features
• 3 A, 100 V.
RDS(ON) = 125 mΩ @ VGS = 10 V
RDS(ON) = 135 mΩ @ VGS = 6 V
• Fast switching speed
• Low gate charge (14 nC typ)
• High performance trench technology for extremely
low RDS(ON)
• High power and current handling capability
5
6 Q1
7
8 Q2
4
3
2
1
Absolute Maximum Ratings TA=25oC unless otherwise noted
Symbol
VDSS
VGSS
ID
PD
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current – Continuous
– Pulsed
Power Dissipation for Dual Operation
Power Dissipation for Single Operation
(Note 1a)
(Note 1a)
(Note 1b)
(Note 1c)
TJ, TSTG
Operating and Storage Junction Temperature Range
Thermal Characteristics
RθJA Thermal Resistance, Junction-to-Ambient
RθJC Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
Package Marking and Ordering Information
Device Marking
Device
Reel Size
FDS3912
FDS3912
13’’
©2001 Fairchild Semiconductor Corporation
Ratings
100
±20
3
20
2
1.6
1.0
0.9
–55 to +175
78
40
Tape width
12mm
Units
V
V
A
W
°C
°C/W
°C/W
Quantity
2500 units
FDS3912 Rev C2(W)
1 page  
Typical Characteristics
10
ID = 3A
8
VDS = 40V
80V
6
60V
4
2
0
0 2 4 6 8 10 12 14 16
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics.
100
10 RDS(ON) LIMIT
1
0.1
0.01
VGS = 10V
SINGLE PULSE
RθJA = 135oC/W
TA = 25oC
100µs
1ms
10ms
100ms
10s
1s
DC
0.001
0.01
0.1 1 10 100
VDS, DRAIN-SOURCE VOLTAGE (V)
1000
Figure 9. Maximum Safe Operating Area.
800
700
600
500
400
300
200
100
CRSS
0
0
CISS
f = 1MHz
VGS = 0 V
COSS
20 40 60 80
VDS, DRAIN TO SOURCE VOLTAGE (V)
100
Figure 8. Capacitance Characteristics.
40
SINGLE PULSE
RθJA = 135°C/W
30 TA = 25°C
20
10
0
0.001
0.01
0.1 1
t1, TIME (sec)
10 100
Figure 10. Single Pulse Maximum
Power Dissipation.
1
0.1
0.01
D = 0.5
0.2
0.1
0.05
0.02
0.01
SINGLE PULSE
RθJA(t) = r(t) + RθJA
RθJA = 135 °C/W
P(pk)
t1
t2
TJ - TA = P * RθJA(t)
Duty Cycle, D = t1 / t2
0.001
0.0001
0.001
0.01
0.1
1
10 100 1000
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.
FDS3912 Rev C2(W)
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet FDS3912.PDF ] | |
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