AT94K10AL-25DQC Datasheet PDF - ATMEL Corporation
| Part Number | AT94K10AL-25DQC | |
| Description | 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller/ up to 36K Bytes of SRAM and On-chip JTAG ICE | |
| Manufacturers | ATMEL Corporation | |
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Features
• Monolithic Field Programmable System Level Integrated Circuit (FPSLIC™)
– AT40K SRAM-based FPGA with Embedded High-performance RISC AVR® Core,
Extensive Data and Instruction SRAM and JTAG ICE
• 5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM™
– 2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM
– High-performance DSP Optimized FPGA Core Cell
– Dynamically Reconfigurable In-System – FPGA Configuration Access Available
On-chip from AVR Microcontroller Core to Support Cache Logic® Designs
– Very Low Static and Dynamic Power Consumption – Ideal for Portable and
Handheld Applications
• Patented AVR Enhanced RISC Architecture
– 120+ Powerful Instructions – Most Single Clock Cycle Execution
– High-performance Hardware Multiplier for DSP-based Systems
– Approaching 1 MIPS per MHz Performance
– C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers
– Low-power Idle, Power-save and Power-down Modes
– 100 µA Standby and Typical 2-3 mA per MHz Active
• Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM
– Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM
– Up to 16 Kbytes x 8 Internal 15 ns Data SRAM
• JTAG (IEEE std. 1149.1 Compliant) Interface
– Extensive On-chip Debug Support
– Limited Boundary-scan Capabilities According to the JTAG Standard (AVR Ports)
• AVR Fixed Peripherals
– Industry-standard 2-wire Serial Interface
– Two Programmable Serial UARTs
– Two 8-bit Timer/Counters with Separate Prescaler and PWM
– One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture
Modes and Dual 8-, 9- or 10-bit PWM
• Support for FPGA Custom Peripherals
– AVR Peripheral Control – 16 Decoded AVR Address Lines Directly Accessible
to FPGA
– FPGA Macro Library of Custom Peripherals
• 16 FPGA Supplied Internal Interrupts to AVR
• Up to Four External Interrupts to AVR
• 8 Global FPGA Clocks
– Two FPGA Clocks Driven from AVR Logic
– FPGA Global Clock Access Available from FPGA Core
• Multiple Oscillator Circuits
– Programmable Watchdog Timer with On-chip Oscillator
– Oscillator to AVR Internal Clock Circuit
– Software-selectable Clock Frequency
– Oscillator to Timer/Counter for Real-time Clock
• VCC: 3.0V - 3.6V
• 3.3V 33 MHz PCI-compliant FPGA I/O
– 20 mA Sink/Source High-performance I/O Structures
– All FPGA I/O Individually Programmable
• High-performance, Low-power 0.35µ CMOS Five-layer Metal Process
• State-of-the-art Integrated PC-based Software Suite including Co-verification
• 5V I/O Tolerant
5K - 40K Gates
of AT40K FPGA
with 8-bit
Microcontroller,
up to 36K Bytes
of SRAM and
On-chip
JTAG ICE
AT94K Series
Field
Programmable
System Level
Integrated
Circuit
Rev. 1138F–FPSLI–06/02
1
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AT94K Series FPSLIC
FPGA Core
Fast, Flexible and
Efficient SRAM
Fast, Efficient
Array and Vector
Multipliers
Cache Logic
Design
Automatic
Component
Generators
The Symmetrical
Array
The AT40K core can be used for high-performance designs, by implementing a variety of com-
pute-intensive arithmetic functions. These include adaptive finite impulse response (FIR)
filters, fast Fourier transforms (FFT), convolvers, interpolators, and discrete-cosine transforms
(DCT) that are required for video compression and decompression, encryption, convolution
and other multimedia applications.
The AT40K core offers a patented distributed 10 ns SRAM capability where the RAM can be
used without losing logic resources. Multiple independent, synchronous or asynchronous,
dual-port or single-port RAM functions (FIFO, scratch pad, etc.) can be created using Atmel’s
macro generator tool.
The AT40K cores patented 8-sided core cell with direct horizontal, vertical and diagonal cell-
to-cell connections implements ultra-fast array multipliers without using any busing resources.
The AT40K core’s Cache Logic capability enables a large number of design coefficients and
variables to be implemented in a very small amount of silicon, enabling vast improvement in
system speed.
The AT40K FPGA core is capable of implementing Cache Logic (dynamic full/partial logic
reconfiguration, without loss of data, on-the-fly) for building adaptive logic and systems. As
new logic functions are required, they can be loaded into the logic cache without losing the
data already there or disrupting the operation of the rest of the chip; replacing or complement-
ing the active logic. The AT40K FPGA core can act as a reconfigurable resource within the
FPSLIC environment.
The AT40K is capable of implementing user-defined, automatically generated, macros; speed
and functionality are unaffected by the macro orientation or density of the target device. This
enables the fastest, most predictable and efficient FPGA design approach and minimizes
design risk by reusing already proven functions. The Automatic Component Generators work
seamlessly with industry-standard schematic and synthesis tools to create fast, efficient
designs.
The patented AT40K architecture employs a symmetrical grid of small yet powerful cells con-
nected to a flexible busing network. Independently controlled clocks and resets govern every
column of four cells. The FPSLIC device is surrounded on three sides by programmable I/Os.
Core usable gate counts range from 5,000 to 40,000 gates and 436 to 2,864 registers. Pin
locations are consistent throughout the FPSLIC family for easy design migration in the same
package footprint.
The Atmel AT40K FPGA core architecture was developed to provide the highest levels of per-
formance, functional density and design flexibility. The cells in the FPGA core array are small,
efficient and can implement any pair of Boolean functions of (the same) three inputs or any
single Boolean function of four inputs. The cell’s small size leads to arrays with large numbers
of cells. A simple, high-speed busing network provides fast, efficient communication over
medium and long distances.
At the heart of the Atmel FPSLIC architecture is a symmetrical array of identical cells. The
array is continuous from one edge to the other, except for bus repeaters spaced every four
cells, see Figure 3. At the intersection of each repeater row and column is a 32 x 4 RAM block
accessible by adjacent buses. The RAM can be configured as either a single-ported or dual-
ported RAM, with either synchronous or asynchronous operation.
Rev. 1138F–FPSLI–06/02
5
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| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ AT94K10AL-25DQC.PDF Datasheet ] | |
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Featured Datasheets
| Part Number | Description | MFRS |
| AT94K10AL-25DQC | The function is 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller/ up to 36K Bytes of SRAM and On-chip JTAG ICE. ATMEL Corporation | |
| AT94K10AL-25DQI | The function is 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller/ up to 36K Bytes of SRAM and On-chip JTAG ICE. ATMEL Corporation | |
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