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PDF AT94S40AL-25BQC Data sheet ( Hoja de datos )
| Número de pieza | AT94S40AL-25BQC | |
| Descripción | Secure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller/ up to 36 Kbytes of SRAM and On-chip Program Storage EEPROM | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Multichip Module Containing Field Programmable System Level Integrated Circuit
(FPSLIC™) and Secure Configuration EEPROM Memory
• 512 Kbits to 1 Mbit of Configuration Memory with Security Protection and In-System
Programming (ISP)
• Field Programmable System Level Integrated Circuit (FPSLIC)
– AT40K SRAM-based FPGA with Embedded High-performance RISC AVR® Core and
Extensive Data and Instruction SRAM
• 5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM™
– 2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM
– High-performance DSP Optimized FPGA Core Cell
– Dynamically Reconfigurable In-System – FPGA Configuration Access Available
On-chip from AVR Microcontroller Core to Support Cache Logic® Designs
– Very Low Static and Dynamic Power Consumption – Ideal for Portable and
Handheld Applications
• Patented AVR Enhanced RISC Architecture
– 120+ Powerful Instructions – Most Single Clock Cycle Execution
– High-performance Hardware Multiplier for DSP-based Systems
– Approaching 1 MIPS per MHz Performance
– C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers
– Low-power Idle, Power-save, and Power-down Modes
– 100 µA Standby and Typical 2-3 mA per MHz Active
• Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM
– Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM
– Up to 16 Kbytes x 8 Internal 15 ns Data SRAM
• JTAG (IEEE Std. 1149.1 Compliant) Interface
– Extensive On-chip Debugging Support
– Limited Boundary-scan Capabilities According to the JTAG Standards (AVR Ports)
• AVR Fixed Peripherals
– Industry-standard 2-wire Serial Interface
– Two Programmable Serial UARTs
– Two 8-bit Timer/Counters with Separate Prescaler and PWM
– One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture
Modes and Dual 8-, 9- or 10-bit PWM
• Support for FPGA Custom Peripherals
– AVR Peripheral Control – Up to 16 Decoded AVR Address Lines Directly
Accessible to FPGA
– FPGA Macro Library of Custom Peripherals
• Up to 16 FPGA Supplied Internal Interrupts to AVR
• Up to Four External Interrupts to AVR
• 8 Global FPGA Clocks
– Two FPGA Clocks Driven from AVR Logic
– FPGA Global Clock Access Available from FPGA Core
• Multiple Oscillator Circuits
– Programmable Watchdog Timer with On-chip Oscillator
– Oscillator to AVR Internal Clock Circuit
– Software-selectable Clock Frequency
– Oscillator to Timer/Counter for Real-time Clock
• VCC: 3.0V - 3.6V
• 5V Tolerant I/O
• 3.3V 33 MHz PCI Compliant FPGA I/O
– 20 mA Sink/Source High-performance I/O Structures
– All FPGA I/O Individually Programmable
• High-performance, Low-power 0.35µ CMOS Five-layer Metal Process
• State-of-the-art Integrated PC-based Software Suite including Co-verification
Secure
5K - 40K Gates
of AT40K FPGA
with 8-bit
Microcontroller,
up to 36 Kbytes
of SRAM and
On-chip
Program
Storage
EEPROM
AT94S
Secure Series
Programmable
SLI
Rev. 2314D–FPSLI–2/04
1
1 page  
Bit Format
Start and Stop
Conditions
Acknowledge Bit
AT94S Secure Family
Again, the Acknowledge Bit is asserted on the cSDA line by the receiving device on a
byte-by-byte basis.
The factory blanks devices to all zeros before shipping. The array cannot otherwise be
“initialized” except by explicitly writing a known value to each location using the serial
protocol described herein.
Data on the cSDA pin may change only during the cSCK Low time; whereas Start and
Stop Conditions are identified as transitions during the cSCK High time.
Write Instruction Message Format
START
DEVICE MS EEPROM (NEXT) EEPROM LS EEPROM DATA
CONDITION ADDRESS ADDRESS BYTE ADDRESS BYTE ADDRESS BYTE BYTE 1
DATA STOP
BYTE n CONDITION
ACK BIT
(CONFIGURATOR)
Current Address Read (Extended to Sequential Read) Instruction Message Format
START
CONDITION
DEVICE
ADDRESS
DATA
BYTE 1
DATA
BYTE n
STOP
CONDITION
ACK BIT
ACK BIT
(CONFIGURATOR) (PROGRAMMER)
The Start Condition is indicated by a high-to-low transition of the cSDA line when the
cSCK line is High. Similarly, the Stop Condition is generated by a low-to-high transition
of the cSDA line when the cSCK line is High, as shown in Figure 2.
The Start Condition will return the device to the state where it is waiting for a Device
Address (its normal quiescent mode).
The Stop Condition initiates an internally timed write signal whose maximum duration is
tWR (refer to AC Characteristics table for actual value). During this time, the Configurator
must remain in programming mode (i.e., SER_EN is driven Low). cSDA and cSCK lines
are ignored until the cycle is completed. Since the write cycle typically completes in less
than tWR seconds, we recommend the use of “polling” as described in later sections.
Input levels to all other pins should be held constant until the write cycle has been
completed.
The Acknowledge (ACK) Bit shown in Figure 2 is provided by the Configurator receiving
the byte. The receiving Configurator can accept the byte by asserting a Low value on
the cSDA line, or it can refuse the byte by asserting (allowing the signal to be externally
pulled up to) a High value on the cSDA line. All bytes from accepted messages must be
terminated by either an Acknowledge Bit or a Stop Condition. Following an ACK Bit,
when the cSDA line is released during an exchange of control between the Configurator
and the programmer, the cSDA line may be pulled High temporarily due to the open-col-
lector output nature of the line. Control of the line must resume before the next rising
edge of the clock.
2314D–FPSLI–2/04
5
5 Page 
AT94S Secure Family
SEQUENTIAL READ: Sequential Reads follow either a Current Address Read or a
Random Address Read. After the programmer receives a Data Byte, it may respond
with an Acknowledge Bit. As long as the Configurator receives an Acknowledge Bit, it
will continue to increment the Data Byte address and serially clock out sequential Data
Bytes until the memory address limit is reached.(1) The Sequential Read instruction is
terminated when the programmer does not respond with an Acknowledge Bit but
instead generates a Stop Condition following the receipt of a Data Byte.
Programmer Functions
Note:
1. If an ACK is sent by the programmer after the data in the last memory address is sent
by the configurator, the internal address counter will “rollover” to the first byte address
of the memory array and continue to send data as long as an ACK is sent by the
programmer.
The following programmer functions are supported while the Configurator is in program-
ming mode (i.e., when SER_EN is driven Low):
1. Read the Manufacturer’s Code and the Device Code (optional for ISP).
2. Program the device.
3. Verify the device.
In the order given above, they are performed in the following manner.
Reading Manufacturer’s
and Device Codes
On AT17LV010 Configurator, the sequential reading of these bytes are accomplished by
performing a Random Read at EEPROM Address 040000H.
The correct codes are:
Manufacturers Code -Byte 0
1E
Device Code
- Byte 1 F7 AT17LV010
Note: The Manufacturer’s Code and Device Code are read using the byte ordering specified for
Data Bytes; i.e., LSB first, MSB last.
Programming the Device
All the bytes in a given page must be written. The page access order is not important but
it is suggested that the Configurator be written sequentially from address 0. Writing is
accomplished by using the cSDA and cSCK pins.
Important Note on AT94S Series The first byte of data will not be cached for read back during FPGA Configuration (i.e.,
Configurators Programming
when SER_EN is driven High) until the Configurator is power-cycled.
Verifying the Device
All bytes in the Configurator should be read and compared to their intended values.
Reading is done using the cSDA and cSCK pins.
In-System Programming
Applications
The AT94S Series Configurators are in-system (re)programmable (ISP). The example
shown on the following page supports the following programmer functions:
1. Read the Manufacturer’s Code and the Device Code.
2. Program the device.
3. Verify the device data.
While Atmel’s Secure FPSLIC Configurators can be programmed from various sources
(e.g., on-board microcontrollers or PLDs), the applications shown here are designed to
facilitate users of our ATDH2225 Configurator Programming Cable. The typical system
setup is shown in Figure 3.
The pages within the configuration EEPROM can be selectively rewritten.
This document is limited to example implementations for Atmel’s AT94S application.
2314D–FPSLI–2/04
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT94S40AL-25BQC.PDF ] | |
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