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PDF ATF16V8C Data sheet ( Hoja de datos )
| Número de pieza | ATF16V8C | |
| Descripción | High Performance E2 PLD | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ATF16V8C (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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Features
• Industry Standard Architecture
Emulates Many 20-Pin PALs®
Low Cost Easy-to-Use Software Tools
• High Speed Electrically Erasable Programmable Logic Devices
5 ns Maximum Pin-to-Pin Delay
• Low Power - 100 µA Pin-Controlled Power Down Mode Option
• CMOS and TTL Compatible Inputs and Outputs
I/O Pin Keeper Circuits
• Advanced Flash Technology
Reprogrammable
100% Tested
• High Reliability CMOS Process
20 Year Data Retention
100 Erase/Write Cycles
2,000V ESD Protection
200 mA Latchup Immunity
Commercial and Industrial Temperature Ranges
•• Dual-in-Line and Surface Mount Packages in Standard Pinouts
Block Diagram
High
Performance
E2 PLD
ATF16V8C
Note: 1. Includes optional PD control pin.
Pin Configurations
Pin Name Function
CLK Clock
I Logic Inputs
I/O Bidirectional Buffers
OE Output Enable
VCC
+5V Supply
PD Power Down
TSSOP Top View
I/CLK
I1
I2
PD/I3
I4
I5
I6
I7
I8
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 I/O
12 I/O
11 I9/OE
DIP/SOIC
PLCC
ATF16V8C
Top view
Rev. 0425D/V16FC-D–04/98
1 page  
Input Test Waveforms and
Measurement Levels:
ATF16V8C
Output Test Loads:
Commercial
tR, tF < 1.5ns (10% to 90%)
Pin Capacitance (f = 1 MHz, T = 25°C) (1)
Typ
Max
Units
Conditions
CIN 5 8 pF VIN = 0V
COUT
6 8 pF VOUT = 0V
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power Up Reset
The ATF16V8C’s registers are designed to reset during
power up. At a point delayed slightly from VCC crossing
VRST, all registers will be reset to the low state. As a result,
the registered output state will always be high on power-
up.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the un-
certainty of how VCC actually rises in the system, the fol-
lowing conditions are required:
1) The VCC rise must be monotonic, from below .7 volts,
2) After reset occurs, all input and feedback setup times
must be met before driving the clock term high, and
3) The signals from which the clock is derived must re-
main stable during tPR.
Parameter Description
tPR
Power-Up
Reset Time
VRST
Power-Up
Reset
Voltage
Typ
600
3.8
Max Units
1,000 ns
4.5 V
5
5 Page 
Complex Mode Logic Diagram
ATF16V8C
*
* Input not available if power down mode is enabled.
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ATF16V8C.PDF ] | |
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