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PDF ATF20V8B-10JC Data sheet ( Hoja de datos )
| Número de pieza | ATF20V8B-10JC | |
| Descripción | High- Performance EE PLD | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Industry Standard Architecture
– Emulates Many 24-Pin PALs®
– Low Cost Easy-to-Use Software Tools
• High-Speed Electrically Erasable Programmable Logic Devices
– 7.5 ns Maximum Pin-to-Pin Delay
• Several Power Saving Options
Device
ATF20V8B
ICC, Stand-By
50 mA
ICC, Active
55 mA
ATF20V8BQ
35 mA
40 mA
ATF20V8BQL
5 mA
20 mA
• CMOS and TTL Compatible Inputs and Outputs
• Input and I/O Pull-Up Resistors
• Advanced Flash Technology
– Reprogrammable
– 100% Tested
• High Reliability CMOS Process
– 20 Year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latchup Immunity
• Commercial and Industrial Temperature Ranges
• Dual-in-Line and Surface Mount Packages in Standard Pinouts
Block Diagram
High-
Performance
EE PLD
ATF20V8B
Pin Configurations
Pin Name
CLK
I
I/O
OE
*
VCC
Function
Clock
Logic Inputs
Bidirectional Buffers
Output Enable
No Internal Connection
+5V Supply
TSSOP Top View
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 IN
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 IN
13 OE/IN
DIP/SOIC
PLCC Top View
Rev. 0407E–05/98
1
1 page  
Input Test Waveforms and
Measurement Levels
ATF20V8B
Output Test Loads
Commercial
tR, tF < 5 ns (10% to 90%)
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Typ Max
Units
Conditions
CIN
COUT
Note:
58
pF VIN = 0V
68
pF VOUT = 0V
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power Up Reset
The registers in the ATF20V8Bs are designed to reset dur-
ing power up. At a point delayed slightly from VCC crossing
VRST, all registers will be reset to the low state. As a result,
the registered output state will always be high on power-up.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the fol-
lowing conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup times
must be met before driving the clock pin high, and
3. The clock must remain stable during tPR.
Preload of Registered Outputs
The ATF16V8B’s registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC file
preload sequence will be done automatically by most of the
approved programmers after the programming.
Electronic Signature Word
There are 64 bits of programmable memory that are always
available to the user, even if the device is secured. These
bits can be used for user-specific data.
Parameter Description
Typ Max Units
tPR
VRST
Power-Up Reset Time 600 1,000
Power-Up Reset Voltage 3.8 4.5
ns
V
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF20V8B fuse patterns. Once programmed, fuse
verify and preload are inhibited. However, the 64-bit User
Signature remains accessible.
The security fuse should be programmed last, as its effect
is immediate.
Programming/Erasing
Programming/erasing is performed using standard PLD
programmers. For further information, see the Configurable
Logic Databook, section titled, “CMOS PLD Programming
Hardware and Software Support.”
5
5 Page 
Simple Mode Logic Diagram
ATF20V8B
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ATF20V8B-10JC.PDF ] | |
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