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PDF ATV2500BQ-25PC Data sheet ( Hoja de datos )
| Número de pieza | ATV2500BQ-25PC | |
| Descripción | High-Speed High-Density UV Erasable Programmable Logic Device | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• High Performance, High Density Programmable Logic Device
– Typical 7 ns Pin-to-Pin Delay
– Fully Connected Logic Array With 416 Product Terms
• Flexible Output Macrocell
– 48 Flip-Flops - Two per Macrocell
– 72 Sum Terms
– All Flip-Flops, I/O Pins Feed In Independently
– Achieves Over 80% Gate Utilization
• Enhanced Macrocell Configuration Selections
– D- or T-Type Flip-Flops
– Product Term or Direct Input Pin Clocking
– Registered or Combinatorial Internal Feedback
• Several Power Saving Options
Device
ATV2500B
ICC, Stand-By
110 mA
ATV2500BQ 30 mA
ATV2500BL 2 mA
ATV2500BQL 2 mA
• Backward Compatible With ATV2500H/L Software
• Proven and Reliable High Speed UV EPROM Process
• Reprogrammable - Tested 100% for Programmability
• 40-Pin Dual-In-Line and 44-Pin Lead Surface Mount Packages
Block Diagram
High-Speed
High-Density
UV Erasable
Programmable
Logic Device
ATV2500B
Pin Configurations
Pin Name
IN
CLK/IN
I/O
I/O 0,2,4..
I/O 1,3,5..
GND
VCC
Function
Logic Inputs
Pin Clock and
Input
Bidirectional
Buffers
“Even” I/O Buffers
“Odd” I/O Buffers
Ground
+5V Supply
Note:
For ATV2500BQ and
ATV2500BQL (PLCC/LCC
package only) pin 4 and
pin 26 connections are not
required.
DIP
LCC/PLCC
CLK/IN
IN
IN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
VCC
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
IN
IN
IN
IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 IN
39 IN
38 IN
37 IN
36 I/O6
35 I/O7
34 I/O8
33 I/O9
32 I/O10
31 I/O11
30 GND
29 I/O23
28 I/O22
27 I/O21
26 I/O20
25 I/O19
24 I/O18
23 IN
22 IN
21 IN
Rev. 0249F–06/98
1
1 page  
Output Logic, Registered(1)
ATV2500B
Output Logic, Combinatiorial(1)
Note: 1. These diagrams show equivalent logic functions, not necessarily the actual circuit implementation.
S2 = 0
S1 S0
00
10
11
Terms in
D/T1
D/T2
84
12 4(1)
84
Output Configuration
Registered (Q1); Q2 FB
Registered (Q1); Q2 FB
Registered (Q1); D/T2 FB
S3 Ouput Configuration
0 Active Low
1 Active High
S4 Register 1 Type
0D
1T
S6 Q1 CLOCK
0 CK1
1 CK1 • PIN1
S7 Q2 CLOCK
0 CK2
1 CK2 • PIN1
S5
X
X
X
1
0
Note:
S2 = 1
Terms in
S1 S0 D/T1 D/T2 Output Configuration
0
0
4(1)
4
Combinatorial (8 Terms);
Q2 FB
0
1
4
4
Combinatorial (4 Terms);
Q2 FB
1
0
4(1)
4(1)
Combinatorial (12 Terms);
Q2 FB
1
1
4(1)
4
Combinatorial (8 Terms);
D/T2 FB
1
1
4
4
Combinatorial (4 Terms);
D/T2 FB
1. These four terms are shared with D/T1.
Clock Option
S5 Register 2 Type
0D
1T
5
5 Page 
ATV2500B
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of ATV2500B fuse patterns. Once programmed, the out-
puts will read programmed during verify. The security
fuse should be programmed last, as its effect is immediate.
The security fuse also inhibits Preload and Q2 observabil-
ity.
Atmel CMOS PLDs
The ATV2500Bs utilize an advanced 0.65-micron CMOS
EPROM technology. This technology's state of the art fea-
tures are the optimum combination for PLDs:
• CMOS technology provides high speed, low power, and
high noise immunity.
• EPROM technology is the most cost effective method for
producing PLDs - surpassing bipolar fusible link
technology in low cost, while providing the necessary
reprogrammability.
• EPROM reprogrammability, which is 100% tested before
shipment, provides inherently better programmability and
reliability than one-time fusible PLDs.
Using the ATV2500Bs Many Advanced
Features
The ATV2500Bs advanced flexibility packs more usable
gates into 44 leads than other PLDs. Some of the
ATV2500Bs key features are:
• Fully Connected Logic Array -
Each array input is always available to every product term.
This makes logic placement a breeze.
• Selectable D- and T-Type Registers -
Each ATV2500B flip-flop can be individually configured as
either D- or T-type. Using the T-type configuration, JK and
SR flip-flops are also easily created. These options allow
more efficient product term usage.
• Buried Combinatorial Feedback -
Each macrocell's Q2 register may be bypassed to feed its
input (D/T2) directly back to the logic array. This provides
further logic expansion capability without using precious pin
resources.
• Selectable Synchronous/Asynchronous Clocking -
Each of the ATV2500Bs flip-flops has a dedicated clock
product term. This removes the constraint that all registers
use the same clock. Buried state machines, counters and
registers can all coexist in one device while running on sep-
arate clocks. Individual flip-flop clock source selection fur-
ther allows mixing higher performance pin clocking and
flexible product term clocking within one design.
• A Total of 48 Registers -
The ATV2500B provides two flip-flops per macrocell - a
total of 48. Each register has its own clock and reset terms,
as well as its own sum term.
• Independent I/O Pin and Feedback Paths -
Each I/O pin on the ATV2500B has a dedicated input path.
Each of the 48 registers has its own feedback term into the
array as well. These features, combined with individual
product terms for each I/O's output enable, facilitate true bi-
directional I/O design.
• Combinable Sum Terms -
Each output macrocell's three sum terms may be combined
into a single term. This provides a fan in of up to 12 product
terms per sum term with no speed penalty.
Programming Software Support
As with all other Atmel PLDs, several third party PLD devel-
opment software products and programmers will support
the ATV2500Bs.
Several third party programmers will support the
ATV2500B as well. Additionally, the ATV2500B may be
programmed to perform the ATV2500H/Ls functional sub-
set (no T-type flip-flops, pin clocking or D/T2 feedback)
using the ATV2500H/L JEDEC file. In this case, the
ATV2500B becomes a direct replacement or speed
upgrade for the ATV2500H/L (additional GND connections
are required). Please refer to the Programmable Logic
Development Tools section for a complete PLD software
and programmer listing.
Erasure Characteristics
The entire memory array of an ATV2500B is erased after
exposure to ultraviolet light at a wavelength of 2537 Å.
Complete erasure is assured after a minimum of 20 min-
utes exposure using 12,000 µW/cm2 intensity lamps
spaced one inch away from the chip. Minimum erase time
for lamps at other intensity ratings can be calculated from
the minimum integrated erasure dose of 15 W•sec/cm2. To
prevent unintentional erasure, an opaque label is recom-
mended to cover the clear window on any UV erasable
PLD which will be subjected to continuous fluorescent
indoor lighting or sunlight.
11
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| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ATV2500BQ-25PC.PDF ] | |
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