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PDF DM74AS286 Data sheet ( Hoja de datos )
| Número de pieza | DM74AS286 | |
| Descripción | 9-Bit Parity Generator/Checker with Bus-Driver Parity I/O Port | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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October 1986
Revised April 2000
DM74AS286
9-Bit Parity Generator/Checker
with Bus-Driver Parity I/O Port
General Description
These universal, 9-bit parity generators/checkers utilize
advanced Schottky high performance circuitry and feature
odd/even outputs to facilitate operation of either odd or
even parity applications. The word length capability is eas-
ily expanded by cascading.
The DM74AS286 can be used to upgrade the performance
of most systems utilizing the DM74AS280 parity generator/
checker. Although the DM74AS286 is implemented without
expander inputs, the corresponding function is provided by
the availability of an input pin XMIT. XMIT is a control line
which makes parity error output active and parity an input
port when HIGH; when LOW, parity error output is inactive
and parity becomes an output port. In addition, parity I/O
control circuitry contains a feature to keep the I/O port in
the 3-STATE during power UP or DOWN to prevent bus
glitches.
Features
s PNP inputs to reduce bus loading
s Generates either odd or even parity for nine data lines
s Inputs are buffered to lower the drive requirements
s Can be used to upgrade existing systems using MSI
parity circuits
s Cascadable for n-bits
s Switching specifications at 50 pF
s Switching specifications guaranteed over full
temperature and VCC range
s A parity I/O portable to drive bus
Ordering Code:
Order Number Package Number
Package Description
DM74AS286M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74AS286N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Number of Inputs Parity I/O
Parity Mode
(A thru I)
XMIT Error
of
that are HIGH Input Output
Operation
0, 2, 4, 6, 8
N/A H
LH
Parity
1, 3, 5, 7, 9
N/A L
L H Generator
0, 2, 4, 6, 8
H N/A H H
Parity
0, 2, 4, 6, 8
L N/A H
L Checker
1, 3, 5, 7, 9
H N/A H
L
Parity
1, 3, 5, 7, 9
L N/A H H Checker
L = LOW Logic Level
H = HIGH Logic Level
N/A = Not Applicable
© 2000 Fairchild Semiconductor Corporation DS006305
www.fairchildsemi.com
1 page  
Typical Applications (Continued)
Note: Parity format in this configuration is “odd parity”
FIGURE 3. 90-Bit Parity Generator/Checker Implementation
Using Device Expansion Techniques
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet DM74AS286.PDF ] | |
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