DT70V27S Datasheet PDF - Integrated Device Technology
| Part Number | DT70V27S | |
| Description | HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM | |
| Manufacturers | Integrated Device Technology | |
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HIGH-SPEED 3.3V
32K x 16 DUAL-PORT
STATIC RAM
IDT70V27S/L
Features:
x True Dual-Ported memory cells which allow simultaneous
access of the same memory location
x High-speed access
– Industrial: 35ns (max.)
– Commercial: 15/20/25/35/55ns (max.)
x Low-power operation
– IDT70V27S
Active: 500mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V27L
Active: 500mW (typ.)
Standby: 660µW (typ.)
x Separate upper-byte and lower-byte control for bus
matching capability
x Dual chip enables allow for depth expansion without
external logic
Functional Block Diagram
R/WL
UBL
CE0L
CE1L
OEL
LBL
x IDT70V27 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
x M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
x Busy and Interrupt Flags
x On-chip port arbitration logic
x Full on-chip hardware support of semaphore signaling
between ports
x Fully asynchronous operation from either port
x LVTTL-compatible, single 3.3V (±0.3V) power supply
x Available in 100-pin Thin Quad Flatpack (TQFP), 108-pin
Ceramic Pin Grid Array (PGA), and 144-pin Fine Pitch BGA
(fpBGA)
x Industrial temperature range (-40°C to +85°C) is available
for selected speeds
R/WR
UBR
CE0R
CE1R
OER
LBR
I/O8-15L
I/O0-7L
BUSYL (1,2)
I/O
Control
I/O
Control
A14L
A0L
Address
Decoder
A14L
A0L
CE0L
CE1L
OEL
R/WL
32Kx16
MEMORY
ARRAY
70V27
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEM L
NOTES:
INT
(2)
L
M/S (2)
1) BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH).
2) BUSY and INT are non-tri-state totem-pole outputs (push-pull).
©2000 Integrated Device Technology, Inc.
6.011
Address
Decoder
A14R
A0R
CE0R
CE1R
OER
R/WR
I/O8-15R
I/O0-7R
BUSYR(1,2)
A14R
A0R
SEMR
INTR(2)
3603 drw 01
JANUARY 2001
DSC 3603/7
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IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Truth Table I Chip Enable(1,2,3)
Commercial and Industrial Temperature Range
CE CE0
CE1
Mode
VIL VIH Port Selected (TTL Active)
L
< 0.2V
>VCC -0.2V
Port Selected (CMOS Active)
VIH X Port Deselected (TTL Inactive)
X
H >VCC -0.2V
VIL Port Deselected (TTL Inactive)
X Port Deselected (CMOS Inactive)
X
<0.2V
Port Deselected (CMOS Inactive)
NOTES:
1. Chip Enable references are shown above with the actual CE0 and CE1 levels, CE is a reference only.
2. Port "A" and "B" references are located where CE is used.
3. "H" = VIH and "L" = VIL
3603 tbl 02
Truth Table II Non-Contention Read/Write Control
Inputs(1)
Outputs
CE(2)
R/W
OE
UB
LB SEM I/O8-15 I/O0-7
Mode
H
X
X
X
X
H
High-Z
High-Z Deselected: Power-Down
X
X
X
H
H
H
High-Z
High-Z Both Bytes Deselected
L
L
X
L
H
H
DATAIN
High-Z Write to Upper Byte Only
L
L
X
H
L
H
High-Z
DATAIN Write to Lower Byte Only
L
L
X
L
L
H
DATAIN
DATAIN Write to Both Bytes
L H L L H H DATAOUT High-Z Read Upper Byte Only
L H L H L H High-Z DATAOUT Read Lower Byte Only
L H L L L H DATAOUT DATAOUT Read Both Bytes
X
X
H
X
X
X
High-Z
High-Z Outputs Disabled
NOTES:
1. A0L — A14L ≠ A0R — A14R.
2. Refer to Chip Enable Truth Table.
3603 tbl 03
Truth Table III Semaphore Read/Write Control
Inputs(1)
Outputs
CE(2)
R/W
OE
UB
LB SEM I/O8-15 I/O0-7
Mode
H H L X X L DATAOUT DATAOUT Read Data in Semaphore Flag
X H L H H L DATAOUT DATAOUT Read Data in Semaphore Flag
H
↑
X
X
X
L
DATAIN
DATAIN Write I/O0 into Semaphore Flag
X
↑
X
H
H
L
DATAIN
DATAIN Write I/O0 into Semaphore Flag
L X X L X L ______ ______ Not Allowed
L X X X L L ______ ______ Not Allowed
NOTES:
1. There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O15). These eight semaphore flags are addressed by A0-A2.
2. Refer to Chip Enable Truth Table.
3603 tbl 04
5
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| Information | Total 22 Pages | |
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