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Integrated Device Technology - 3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING 2/048 x 36 x 2 4/096 x 36 x 2 8/192 x 36 x 2

Numéro de référence DT72V3654L10PF
Description 3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING 2/048 x 36 x 2 4/096 x 36 x 2 8/192 x 36 x 2
Fabricant Integrated Device Technology 
Logo Integrated Device Technology 





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DT72V3654L10PF fiche technique
3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING
2,048 x 36 x 2
4,096 x 36 x 2
8,192 x 36 x 2
IDT72V3654
IDT72V3664
IDT72V3674
FEATURES
Memory storage capacity:
IDT72V3654 – 2,048 x 36 x 2
IDT72V3664 – 4,096 x 36 x 2
IDT72V3674 – 8,192 x 36 x 2
Clock frequencies up to 100 MHz (6.5ns access time)
Two independent clocked FIFOs buffering data in opposite
directions
Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRB flag functions)
Programmable Almost-Empty and Almost-Full flags; each has five
default offsets (8, 16, 64, 256 and 1,024 )
Serial or parallel programming of partial flags
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
Big- or Little-Endian format for word and byte bus sizes
Retransmit Capability
Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA and CLKB may be asynchronous or coincident
(simultaneous reading and writing of data on a single clock edge
is permitted)
Auto power down minimizes power dissipation
Available in space saving 128-pin Thin Quad Flatpack (TQFP)
Pin and functionally compatible version of the 5V operating
IDT723654/723664/723674
Pin compatible to the lower density parts, IDT72V3624/72V3634/
72V3644
Industrial temperature range (–40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
MRS1
PRS1
FFA/IRA
AFA
Port-A
Control
Logic
FIFO1,
Mail1
Reset
Logic
36
Mail 1
Register
36
RAM ARRAY
2,048 x 36
36
4,096 x 36
8,192 x 36
FIFO1
Write
Pointer
Read
Pointer
Status Flag
Logic
MBF1
36
EFB/ORB
AEB
FS2
FS0/SD
FS1/SEN
A0-A35
EFA/ORA
AEA
Programmable Flag
Offset Registers
Timing
Mode
13
FIFO2
Status Flag
Logic
FWFT
B0-B35
FFB/IRB
AFB
RT1
RTM
RT2
36
FIFO1 and
FIFO2
Retransmit
Logic
MBF2
Read
Pointer
Write
Pointer
RAM ARRAY
36 2,048 x 36
4,096 x 36
8,192 x 36
Mail 2
Register
36
36
FIFO2,
Mail2
Reset
Logic
MRS2
PRS2
Port-B
Control
Logic
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
4664 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2003
DSC-4664/4

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DT72V3654L10PF 3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING 2/048 x 36 x 2 4/096 x 36 x 2 8/192 x 36 x 2 Integrated Device Technology
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