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74AHC3GU04DP fiches techniques PDF

NXP Semiconductors - high-speed Si-gate CMOS device

Numéro de référence 74AHC3GU04DP
Description high-speed Si-gate CMOS device
Fabricant NXP Semiconductors 
Logo NXP Semiconductors 





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74AHC3GU04DP fiche technique
74AHC3GU04
Inverter
Rev. 01 — 5 March 2004
Product data sheet
1. General description
The 74AHC3GU04 is a high-speed Si-gate CMOS device. This device provides the
inverting single stage function.
2. Features
s Symmetrical output impedance
s High noise immunity
s ESD protection:
x HBM EIA/JESD22-A114-A exceeds 2000 V
x MM EIA/JESD22-A115-A exceeds 200 V
x CDM EIA/JESD22-C101 exceeds 1000 V.
s Low power dissipation
s Balanced propagation delays
s SOT505-2 and SOT765-1 package
s Output capability ±8 mA drive
s Specified from 40 °C to +85 °C and from 40 °C to +125 °C.
3. Quick reference data
Table 1: Quick reference data
GND = 0 V; Tamb = 25 °C; tr = tf 3.0 ns.
Symbol Parameter
Conditions
Min Typ Max Unit
tPHL, tPLH
propagation delay nA to nY VCC = 5 V;
CL = 15 pF
- 2.5 5.5 ns
CI input capacitance
CPD power dissipation
capacitance
-
[1] -
[2]
3.0 10
4-
pF
pF
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
[2] The condition is VI = GND to VCC.

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