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PDF 74ALVC164245 Data sheet ( Hoja de datos )
| Número de pieza | 74ALVC164245 | |
| Descripción | 16-bit dual supply translating transceiver | |
| Fabricantes | NXP Semiconductors | |
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74ALVC164245
16-bit dual supply translating transceiver; 3-state
Rev. 8 — 15 March 2012
Product data sheet
1. General description
The 74ALVC164245 is a high-performance, low-power, low-voltage, Si-gate CMOS
device, superior to most advanced CMOS compatible TTL families.
The 74ALVC164245 is a 16-bit (dual octal) dual supply translating transceiver featuring
non-inverting 3-state bus compatible outputs in both send and receive directions. It is
designed to interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply
environment.
This device can be used as two 8-bit transceivers or one 16-bit transceiver.
The direction control inputs (1DIR and 2DIR) determine the direction of the data flow.
nDIR (active HIGH) enables data from nAn ports to nBn ports. nDIR (active LOW) enables
data from nBn ports to nAn ports. The output enable inputs (1OE and 2OE), when HIGH,
disable both nAn and nBn ports by placing them in a high-impedance OFF-state. Pins
nAn, nOE and nDIR are referenced to VCC(A) and pins nBn are referenced to VCC(B).
In suspend mode, when one of the supply voltages is zero, there will be no current flow
from the non-zero supply towards the zero supply. The nAn-outputs must be set 3-state
and the voltage on the A-bus must be smaller than Vdiode (typical 0.7 V). VCC(B) VCC(A)
(except in suspend mode).
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range:
3 V port (VCC(A)): 1.5 V to 3.6 V
5 V port (VCC(B)): 1.5 V to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Control inputs voltage range from 2.7 V to 5.5 V
Inputs accept voltages up to 5.5 V
High-impedance outputs when VCC(A) or VCC(B) = 0 V
Complies with JEDEC standard JESD8-B/JESD36
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from 40 C to +85 C and 40 C to +125 C
1 page  
NXP Semiconductors
74ALVC164245
16-bit dual supply translating transceiver; 3-state
terminal 1
index area
D1 A32 A31 A30 A29 A28 A27 D4
A1 D5
B20 B19 B18
D8 A26
A2
B1
A3
B2
A4
B3
A5
B4
A6
B5
A7
B6
A8
B7
A9
74ALVC164245
GND(1)
A25
B17
A24
B16
A23
B15
A22
B14
A21
B13
A20
B12
A19
B11
A18
A10 D6
B8 B9 B10
D7 A17
D2 A11 A12 A13 A14 A15 A16 D3
Transparent top view
001aai851
(1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to
GND.
Fig 4. Pin configuration SOT1134-2 (HXQFN60)
74ALVC164245
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 15 March 2012
© NXP B.V. 2012. All rights reserved.
5 of 20
5 Page 
NXP Semiconductors
74ALVC164245
16-bit dual supply translating transceiver; 3-state
Table 7. Dynamic characteristics …continued
GND = 0 V; tr = tf 2.5 ns; CL = 50 pF; for test circuit see Figure 7.
Symbol Parameter
Conditions
Tamb = 40 C to +85 C
Min Typ[1] Max
CPD power
5 V port: nAn to nBn;
[3][4]
dissipation
VCC(B) = 5 V; VCC(A) = 3.3 V
capacitance
outputs enabled
- 30 -
outputs disabled
- 15 -
3 V port: nBn to nAn;
[3][4]
VCC(B) = 5 V; VCC(A) = 3.3 V
outputs enabled
- 40 -
outputs disabled
-5-
Tamb = 40 C to +125 C Unit
Min Max
- - pF
- - pF
- - pF
- - pF
[1] All typical values are measured at nominal voltage for VCC(B) and VCC(A) and at Tamb = 25 C.
[2] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
[4] The condition is VI = GND to VCC.
11. AC waveforms
nAn, nBn
input
VI
GND
VOH
nBn, nAn
output
VOL
tPHL
VM
VM
tPLH
001aaa792
Fig 5.
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Input (nAn, nBn) to output (nBn, nAn) propagation delays
74ALVC164245
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 15 March 2012
© NXP B.V. 2012. All rights reserved.
11 of 20
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