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74ALVCH162373T fiches techniques PDF

Fairchild Semiconductor - Low Voltage 16-Bit Transparent Latch with Bushold and 26 Series Resistors in Outputs

Numéro de référence 74ALVCH162373T
Description Low Voltage 16-Bit Transparent Latch with Bushold and 26 Series Resistors in Outputs
Fabricant Fairchild Semiconductor 
Logo Fairchild Semiconductor 





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74ALVCH162373T fiche technique
November 2001
Revised November 2001
74ALVCH162373
Low Voltage 16-Bit Transparent Latch with Bushold
and 26Series Resistors in Outputs
General Description
The ALVCH162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear to be transparent to the data when the Latch enable
(LE) is HIGH. When LE is LOW, the data that meets the
setup time is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the out-
puts are in a high impedance state.
The ALVCH162373 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
The ALVCH162373 is also designed with 26series resis-
tors in the outputs. This design reduces line noise in appli-
cations such as memory address driver, clock drivers and
bus transceivers/transmitters.
The 74ALVCH162373 is designed for low voltage (1.65V to
3.6V) VCC applications with output compatibility up to 3.6V.
The 74ALVCH162373 is fabricated with an advanced
CMOS technology to achieve high speed operation while
maintaining low CMOS power dissipation.
Features
s 1.65V to 3.6V VCC supply operation
s 3.6V tolerant control inputs and outputs
s Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
s 26series resistors in outputs
s tPD (In to On)
3.8 ns max for 3.0V to 3.6V VCC
5.0 ns max for 2.3V to 2.7V VCC
9.0 ns max for 1.65V to 1.95V VCC
s Uses patented noise/EMI reduction circuitry
s Latchup conforms to JEDEC JED78
s ESD performance:
Human body model > 2000V
Machine model > 200V
Ordering Code:
Ordering Number Package Number
Package Description
74ALVCH162373T
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OEn
LEn
I0I15
O0O15
Description
Output Enable Input (Active LOW)
Latch Enable Input
Bushold Inputs
Outputs
© 2001 Fairchild Semiconductor Corporation DS500708
www.fairchildsemi.com

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