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PDF JDP2S01T Data sheet ( Hoja de datos )
| Número de pieza | JDP2S01T | |
| Descripción | UHF~VHF Band RF Attenuator Applications | |
| Fabricantes | Toshiba Semiconductor | |
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ISP1362
Single-chip Universal Serial Bus On-The-Go controller
Rev. 03 — 06 January 2004
Product data
1. General description
The ISP1362 is a single-chip Universal Serial Bus (USB) On-The-Go (OTG) controller
integrated with the advanced Philips Slave Host Controller (PSHC) and the Philips
ISP1181B Device Controller (DC). The USB OTG controller is compliant with
On-The-Go Supplement to the USB 2.0 Specification Rev. 1.0a. The host and device
controllers are compliant with Universal Serial Bus Specification Rev. 2.0, supporting
data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s).
The ISP1362 has two USB ports: port 1 and port 2. Port 1 can be hardware
configured to function as a downstream port, an upstream port or an OTG port
whereas port 2 can only be used as a downstream port. The OTG port can switch
roles from host to peripheral, or from peripheral to host. The OTG port can become a
host through the Host Negotiation Protocol (HNP) as specified in the OTG
supplement.
A USB product with OTG capability can function either as a host or as a peripheral.
For instance, with this dual-role capability, a Personal Computer (PC) peripheral such
as a printer may switch roles from a peripheral to a host for connecting to a digital
camera so that the printer can print pictures taken by the camera without using a PC.
When a USB product with OTG capability is inactive, the USB interface is turned off.
This feature has made OTG a technology well-suited for use in portable
devices—such as, Personal Digital Assistant (PDA), Digital Still Camera (DSC) and
mobile phone—in which power consumption is a concern. The ISP1362 is an OTG
controller designed to perform such functions.
2. Features
s Complies fully with:
x Universal Serial Bus Specification Rev. 2.0
x On-The-Go Supplement to the USB 2.0 Specification Rev. 1.0a
s Supports data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
s Adapted from Open Host Controller Interface Specification for USB Release 1.0a
s USB OTG:
x Supports Host Negotiation Protocol (HNP) and Session Request Protocol
(SRP) for OTG dual-role devices
x Provides status and control signals for software implementation of HNP and
SRP
x Provides programmable timers required for HNP and SRP
x Supports built-in and external source of VBUS
x Output current of the built-in charge pump is adjustable by using an external
capacitor
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12 MHz CLKOUT
X2 X1
44 43 38
RESET
32
POWER-ON
RESET
internal
reset
HC BUFFER
MEMORY
PLL
H_SUSPEND/
H_WAKEUP
16
D0 to D15
RD
CS
WR
A0
A1
DACK1
DACK2
DREQ1
DREQ2
INT1
INT2
TEST0
TEST1
TEST2
33
2, 3,
5 to 8,
10 to 13,
15 to 18,
63, 64
ADVANCED PHILIPS
SLAVE HOST
CONTROLLER
to system
clock
20
21
22
61 BUS
62 INTERFACE
28
29
24
25
30
31
ON-THE-GO
CONTROLLER
PHILIPS DEVICE
CONTROLLER
23
59
60
1, 9, 19, 27,
37, 57
51
DC BUFFER
MEMORY
4, 14, 26,
40, 52, 58 34
GOODLINK
39 45
48
ISP1362
OVERCURRENT
PROTECTION
USB
TRANSCEIVER
56 VDD_5V
35 H_PSW1
36 H_PSW2
42
H_OC1
41
H_OC2
46 H_DM2
47 H_DP2
OTG
TRANSCEIVER
49 OTG_DM1
50 OTG_DP1
CHARGE
PUMP
55 VBUS
54 53
004aaa044
DGND
AGND VCC D_SUSPEND/
D_WAKEUP
GL ID CP_CAP2 CP_CAP1
OTGMODE
Fig 1. Block diagram.
5 Page 
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Table 2: Pin description…continued
Symbol[1]
Pin
Ball
Type[2]
LQFP64 TFBGA64
H_PSW2
36
G9
O
Description
connects to the external PMOS switch
LOW — switches ON the PMOS providing VBUS to the downstream
port
HIGH — switches OFF the PMOS
when not in use, leave this pin open
open-drain output
DGND
37 G10 - digital ground
CLKOUT
38
F9
O programmable clock output; the default clock frequency is 12 MHz and
can be varied from 3 MHz to 48 MHz
push-pull output
GL 39 F10 O GoodLink LED indicator output; the LED is OFF by default, blinks ON
upon USB traffic
open-drain output; 4 mA
VCC
40 E9
- supply voltage (3.3 V); it is recommended to connect a decoupling
capacitor of 0.01 µF
H_OC2
H_OC1
X1
41 E10 I overcurrent sense input for downstream port 2; both the digital and
analog overcurrent inputs can be used for port 2, depending on the
hardware mode register setting; when not in use, it is recommended to
connect this pin to the VDD_5V pin
42 D9
I overcurrent sensing input for downstream port 1; both the digital and
analog overcurrent inputs can be used for port 1, depending on the
hardware mode register setting; when not in use, it is recommended to
connect this pin to the VDD_5V pin
43 D10 AI crystal input; connected directly to a 12 MHz crystal; when this pin is
connected to an external clock oscillator, leave pin X2 open
X2
44 C9
AO crystal output; connected directly to a 12 MHz crystal; when pin X1 is
connected to an external clock oscillator, leave this pin open
OTGMODE
45
C10
I
to select whether port 1 is operating in the OTG or non-OTG mode;
see Table 8
input with hysteresis
H_DM2
46 B9
AI/O
downstream D− signal; host only, port 2; when not in use, leave this
pin open and set bit ConnectPullDown_DS2 of the
HcHardwareConfiguration register
H_DP2
47 B10 AI/O downstream D+ signal; host only, port 2; when not in use, leave this
pin open and set bit ConnectPullDown_DS2 of the
HcHardwareConfiguration register
ID 48 A10 I input pin for sensing OTG ID; the status of this input pin is reflected in
the OTGStatus register (bit 0); see Table 8
input with hysteresis
OTG_DM1
49
A9
AI/O
D− signal of the OTG port, the downstream host port 1 or the
upstream device port; when not in use, leave this pin open and set
bit ConnectPullDown_DS1 of the HcHardwareConfiguration register[3]
OTG_DP1
50
B8
AI/O
D+ signal of the OTG port, the downstream host port 1 or the
upstream device port; when not in use, leave this pin open and set
bit ConnectPullDown_DS1 of the HcHardwareConfiguration register[3]
9397 750 12337
Product data
Rev. 03 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11 of 150
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