|
|
PDF K5P2880YCM Data sheet ( Hoja de datos )
| Número de pieza | K5P2880YCM | |
| Descripción | Multi-Chip Package MEMORY 128M Bit 16Mx8 Nand Flash Memory / 8M Bit 1Mx8/512Kx16 Full CMOS SRAM | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de K5P2880YCM (archivo pdf) en la parte inferior de esta página. Total 29 Páginas | ||
|
No Preview Available !
K5P2880YCM - T085
Document Title
Multi-Chip Package MEMORY
128M Bit (16Mx8) Nand Flash Memory / 8M Bit (1Mx8/512Kx16) Full CMOS SRAM
Revision History
Revision No. History
0.0 Initial issue.
Draft Date
Jun. 11th 2001
Remark
Advanced
Information
Note : For more detailed features and specifications including FAQ, please refer to Samsungs’ web site.
http://samsungelectronics.com/semiconductors/products/products_index.html
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
- 1 - Revision 0.0
June. 2001
1 page  
K5P2880YCM - T085
Table 2. FLASH MEMORY OPERATIONS TABLE
CLE
ALE
CE
WE
RE
WP
Mode
HL L
LHL
HX
HX
Read Mode
Command Input
Address Input(3clock)
HL L
LHL
HH
HH
Write Mode
Command Input
Address Input(3clock)
LLL
H H Data Input
LLLH
X Sequential Read & Data Output
L L X H H X During Read(Busy)
X X X X X H During Program(Busy)
X X X X X H During Erase(Busy)
X X(1) X X X L Write Protect
X X H X X 0V/VCC(2) Stand-by
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
Table 3. SRAM OPERATIONS TABLE
1. Word Mode
CS1 CS2 OE WE BYTE SA
HXXX X X
XLXX X X
XXXX X X
L H H H VCC X
L H H H VCC X
L H L H VCC X
L H L H VCC X
L H L H VCC X
L H X L VCC X
L H X L VCC X
L H X L VCC X
Note: X means don′t care. (Must be low or high state)
LB
X
X
H
L
X
L
H
L
L
H
L
2. Byte Mode
CS1 CS2 OE WE BYTE SA
HXXX X X
XLXX X X
L
H
H
H
VSS
SA1)
L
H
L
H
VSS
SA1)
L
H
X
L
VSS
SA1)
Note: X means don′t care.(Must be low or high state)
1. Address input for byte operation.
LB
X
X
DNU
DNU
DNU
UB
X
X
H
X
L
H
L
L
H
L
L
UB
X
X
DNU
DNU
DNU
I/O0~7
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
High-Z
Dout
Din
High-Z
Din
I/O0~7
High-Z
High-Z
High-Z
Dout
Din
I/O8~15
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
Dout
High-Z
Din
Din
I/O8~15
High-Z
High-Z
DNU
DNU
DNU
Mode
Deselected
Deselected
Deselected
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
Lower Byte Write
Upper Byte Write
Word Write
Mode
Deselected
Deselected
Output Disabled
Lower Byte Read
Lower Byte Write
Power
Standby
Standby
Standby
Active
Active
Active
Active
Active
Active
Active
Active
Power
Standby
Standby
Active
Active
Active
- 5 - Revision 0.0
June. 2001
5 Page 
K5P2880YCM - T085
NAND Flash Technical Notes
Invalid Block(s)
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor-
mation regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality
level or as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the perfor-
mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design
must be able to mask out the invalid block(s) via address mapping. The 1st block of the NAND Flash, however, is fully guaranteed to
be a valid block.
Identifying Invalid Block(s)
All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The invalid
block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid
block has non-FFh data at the column address of 517. Since the invalid block information is also erasable in most cases, it is impos-
sible to recover the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based
on the original invalid block information and create the invalid block table via the following suggested flow chart(Figure 10). Any
intentional erasure of the original invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Create (or update)
Invalid Block(s) Table
No
*Check "FFh" ?
Check "FFh" at the column address 517
of the 1st and 2nd page in the block
Yes
No
Last Block ?
Yes
End
Figure 10. Flow chart to create invalid block table
- 11 -
Revision 0.0
June. 2001
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet K5P2880YCM.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| K5P2880YCM | Multi-Chip Package MEMORY 128M Bit 16Mx8 Nand Flash Memory / 8M Bit 1Mx8/512Kx16 Full CMOS SRAM | Samsung semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |