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PDF XR-T6166 Data sheet ( Hoja de datos )
| Número de pieza | XR-T6166 | |
| Descripción | Codirectional Digital Data Processor | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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...the analog plus companyTM
XR-T6166
Codirectional Digital Data
Processor
FEATURES
D Low Power CMOS Technology
D All Receiver and Transmitter Inputs and Outputs are
TTL Compatible
D Transmitter Inhibits Bipolar Violation Insertion for
Transmission of Alarm Conditions
D Alarm Output Indicates Loss of Received Bipolar
Violations
D Tolerance of 125µs Variance of Data Transfer
Timing in Both Transmit and Receive Paths
Allows Operation in Plesiochronous Networks
D Both Receiver and Transmitter Perform Byte
Insertion or Deletion in Response to Local Clock
Slips and Provide Outputs Indicating Slip Logic
Activity
APPLICATIONS
Dec 2010
D CCITT G.703 Compliant 64kbps Codirectional
Interface
D Performs the Digital and Analog Functions for
a Complete 64kbps Data Adaption Unit (DAU) When
Used With the XR-T6164
GENERAL DESCRIPTION
The XR-T6166 is a CMOS device which contains the
digital circuitry necessary to interface both directions of a
64kbps data stream to 2.048Mbps transmit and receive
PCM time-slots. The XR-T6166 and the companion
XR-T6164 line interface chip together form a CCITT
G.703 compliant 64kbps codirectional interface.
The XR-T6166 contains separate transmit and receive
sections. The transmitter transforms 8 bit serial data from
a 2.048Mbps time-slot into an encoded 64kbps data
stream. The receiver , which performs the reverse
operation, decodes the 64kbps data, extracts a clock
signal, and then outputs the data to a 2.048Mbps
time-slot. The XR-T6166 provides features which allow
the repetitions and deletions of both received and
transmitted data as clock skews and transients occur .
These slip occurrences are indicated by byte insertion
and deletion flags. Outputs are also provided for
extracted receive clock and clock recovery circuit loss of
lock.
ORDERING INFORMATION
Part No.
XR-T6166CD
Package
28 Lead 300 Mil JEDEC SOIC
Operating
Temperature Range
0°C to +70°C
XR-T6166ID
28 Lead 300 Mil JEDEC SOIC
–40°C to 85°C
Rev. 2.03
E2010
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z (510) 668-7010
1
1 page  
XR-T6166
ELECTRICAL CHARACTERISTICS
Test Conditions: VDD = 5V $10%, TA = 25°C, Unless Otherwise Specified
Symbol Parameter
DC Electrical Characteristics
VIH Logic 1
VIL Logic 0
VDD Supply
IDD Supply Current
IIL Input Leakage
VOL
VOH
AC Electrical Characteristics
General
tr, tf
Output Rise/Fall Time
Receiver
tRS
tRH
tDRS
tDRH
tRXD
tPW
tRXH
tRXL
tRXCLK
RX2MHz Rising Edge to TS
Rising Edge Set Up Time
RX2MHz Rising Edge to TS
Falling Edge Hold Time
TS Rising Edge to Leading Edge
of PCMOUT D0 Bit Delay
TS Falling Edge to Trailing Edge
of PCMOUT D7 Bit Hold Time
RX2MHz Rising Egde to
PCMOUT Bits D1 Through D6
Rising Edge Delay
PCMOUT Pulse Width
RX2MHz High Time
RX2MHz Low Time
RX2MHz Period
Transmitter
tTS TS Rising Edge to TX2MHz Set
Up Time
tTH TS Falling Edge to TX2MHz Hold
Time
tDS PCMIN Edge to TX2MHz Set Up
Time
tDH PCMIN Edge to TX2MHz Hold
Time
tTXH
TX2MHz High Time
tTXL
TX2MHz Low Time
tTXCLK TX2MHz Period
Min.
2.4
4.5
2.4
0
0
0
20
0
100
100
Typ. Max.
0.4
5.5
500
1
0.4
20
tRXL-
100
tRXL-
100
10
10
10
488
244
244
488
tTXL-
100
tTXL-
100
244
244
488
Unit Conditions
V
V
V
µA Dynamic Supply Current
µA
V At 1.6mA
mA At 0.4mA
ns All Outputs
ns Figure 3
ns Figure 3
ns Figure 3
ns Figure 3
ns Figure 3
ns Figure 3
ns Figure 3
ns Figure 3
ns $100ppm
ns Figure 5
ns Figure 5
ns Figure 5
ns Figure 5
ns Figure 5
ns Figure 5
ns $100ppm
Rev. 2.03
5
5 Page 
XR-T6166
Transmitter Code Conversion
Figure 8 shows the transmitter code conversion process
that CCITT G.703 specifies for a 64kbps codirectional
interface.
Step 1 - A 64kbps bit period is divided into four unit
intervals.
Step 2 - A binary 1 is coded as a 1100.
Step 3 - A binary 0 is coded as a 1010.
Step 4 - The binary signal is converted into a three-level
signal by alternating the polarity of consecutive blocks.
Step 5 - The alternation in polarity of the blocks is violated
every eighth block. The violation block marks the last bit
in an octet.
Bit Number 7 8 1 2 3 4 5 6 7 8 1
64kbps data
10
0
10
0
1
11
01
Steps 1-3
StepÌÌÌ4 ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
StepÌÌÌ5 ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
Violation
Violation
Octel TimingÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
Figure 8. Transmitter Code Conversion for a 64kbps Bipolar Line Signal
Rev. 2.03
11
11 Page | ||
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| PDF Descargar | [ Datasheet XR-T6166.PDF ] | |
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