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PDF YGV627 Data sheet ( Hoja de datos )
| Número de pieza | YGV627 | |
| Descripción | AVDP3E - Advanced Video Display processor 3 Enhanced | |
| Fabricantes | ETC | |
| Logotipo |  |
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YGV627
AVDP3E
Advanced Video Display processor 3 Enhanced
s OUTLINE
YGV627 is a VDP (Video Display Processor) that realizes higher resolution, multi-color and high speed drawing
by adopting a synchronous DRAM as the video memory, while maintaining the register compatibility with
YGV617B that is used for controlling the high minuteness On Screen Display (OSD).
Since the device is capable of displaying bitmap images with various resolutions ranging from NTSC to SVGA on
the monitors with any size of screen including wide screen, it can be used for controlling OSD for various display
units. Also, it is capable of representation of varied images in accordance with the application because numerous
number of colors can be selected such as the one in the range from 16 to 65536 RGB color display, or natural image
display using YCbCr.
In addition, the existing system can be up-graded easily thanks to the basic features from YGV617B such as a high
speed drawing function, character drawing function, synchronization with external video signal, digital video input /
output function, and hardware cursor display function.
s FEATURES
YGV627 is capable of selecting two modes by using the setting of ENH pin.
For convenience, the case of using ENH pin with LOW level (enabled) is referred to as “expansion mode” in this
document. In the expansion mode, all the functions can be used.
The case of using ENH pin with HIGH level (disabled) is referred to as “compatibility mode”. In the compatibility
mode, the software compatibility with YGV617B is maintained, but the functions enhanced for YGV617B cannot
be used. These modes should be used in accordance with the purpose of the application of this device.
[Display functions]
q Three screen configuration including bitmap screen, sprite cursor screen and external input video screen
(or single color border screen)
q Monitor synchronization frequency, dot clock frequency, and display screen resolution can be specified optionally.
q Display dot clock up to 40 MHz (Example of resolution: NTSC, PAL, VGA, SVGA, NTSC wide, and VGA wide)
q Support with progressive scanning and interlaced scanning
q Resolution of sprite cursor screen is 32 X 32 dots. (The sprite cursor can also be used as cross-hair line cursor.)
q Smooth hardware scroll function
q Upper / lower two division display on the bitmap screen (The two sections can be scrolled independently).
q 256 word X 16 bit CLUT is built-in (The number of display colors of 32768 colors or 65536 colors can be selected.)
q Display colors: 16 palette color, 256 palette color, 32768 RGB color, 65536 RGB color, YCbCr422 (ITU601)
q YCbCr (ITU601) -to-8 bit RGB decoder is built-in.
q α blending function that mixes with external input screen or single color border screen. (64 intensity levels)
q Dot clock generation with built-in PLL circuit
q Generates dot clock that synchronizes with HSYNC of external video signal.
q Generates dot clock that synchronizes with external input clock. (such as sub-carrier clock)
YGV627 CATALOG
CATALOG No.: LSI-4GV627A2
2001.01
1 page  
YGV627
s PIN FUNCTIONS
<CPU interface>
q D15−0 ( I/O: PULL UP )
This is a data bus for connecting with external processor. D15−D8 are not used when the CPU bus with 8 bit type
(when low level is inputted to LWD). At this time, keep the D15−D8 open. These pins are provided with pull-up
resistors respectively.
q A22−1 ( I )
This is an address bus to be connected with external general purpose microcomputer. In the indirect access mode
(high level inputted to DMAP pin), input to A22−A4 pins are ignored when accessing CSREG space.
In the direct access mode (low level inputted to DMAP pin), input to A22−A8 pins are ignored when accessing
CSREG space.
YGV627 can be used as a YGV617B compatible device when A22 and A21 pins are fixed to low level. Unused pins
must be set to low level or high level.
q CSREG ( I )
It is a chip select signal input to register space (I/O). When this chip select signal is active, the read / write pulses
inputted are made valid so that the registers in the YGV627 are accessed.
The function of this pin is the same as that of CSIO pin of YGV617B.
q CSMEM ( I )
This is a chip select signal input pin for video memory port. The read / write pulse inputted while this signal is active
can be used to directly access the video memory controlled by YGV627.
It is possible not to use CSMEM because the video memory can also be accessed from registers. In such case, it is
necessary to input high level to CSMEM pin.
q A0 / WR1, WR0 ( I )
When chip select input is active, these pins control write access to YGV627.
D15−D8 are controlled by A0 / WR1, and D7−D0 by WR0.
When the CPU is 8 bit type, A0 / WR1 functions as CPU address bit 0.
q RD ( I )
When chip select input is active, RD controls read access from YGV627.
D15−D0 are in Output State in the period while both this signal and chip select signals are active.
q READY ( O: PULL UP, 3-state output )
This is data ready signal output to CPU. The READY signal is made low when the internal state of YGV627 is
accessible. READY is a 3-state output. When CSREG or CSMEM (hereafter called CS signals) is not active, it is
high impedance state, and when CS signals is active and RD or WR1, WR0 is not active, high level is outputted
from READY.
Some CPU must use WAIT signal instead of this signal.
A22-A1
CS
A0/WR1, WR0
D15-D0
¯R¯E¯A¯D¯Y¯
Hi-Z
VALID
VALID
Hi-Z
READY signal at write access
5
5 Page 
YGV627
q SYSEL ( I: PULL UP )
This signal selects the source of reference clock to be used in the system.
When low level is inputted to SYSEL, the system clock and dot clock use the same source of the clock. In this case,
the common clock is inputted into DTCKIN. Therefore, there is no need to input clock into SYCKIN. When high
level is inputted to SYSEL, SYCKIN pin input is used as the reference system clock independent from the dot clock.
When SYSEL is used with low level input, be sure to input stable clock into DTCKIN even if the clock produced by
the built-in PLL is used as the dot clock. Since SYSEL is used for selection of a mode, always fix it to either level.
This pin has a pull-up resistor.
The function of this pin is the same as that of VCKS pin of YGV617B.
q DTCKIN ( I ), DTCKOUT ( O )
Crystal is connected to these pins to input dot clock.
When operating the built-in PLL in FSC sync mode, the reference clock is inputted to these pins. At this time, the
clock with multiple of fsc is to be inputted. When PLL function is not used, this input clock is supplied directly to the
CRTC block and displays data control block. When low level is inputted to SYSEL, it is also supplied as the reference
system clock.
When inputted externally generated clock, input it into DTCKIN.
DTCKIN and DTCKOUT are the same as DCKIN and DCKOUT of YGV617B.
DTCKIN
DTCKOUT
q DPLLVSSR, DPLLRREF, DPLLFILT ( Analog )
These pins are used to connect external resistors and capacitors for the built-in PLL that produces dot clock.
When directly using DTCKIN input signal as dot clock without using the built-in PLL, keep DPLLFILT open and
short-circuit between DPLLRREF and DPLLVSSR.
DPLLFILT
3.3KΩ
220pF
DPLLRREF
3.9KΩ
DPLLVSSR
Notes:
1. Arrange the components so that the parasitic capacitance among DPLLFILT, DPLLRREF and DPLLVSSR is
minimized and the signals do not cross each other.
2. PLL may not lock if there is a time difference between the rising moment of AVDD (for PLL) and the rising
moment of VDD (for Digital Logic).
11
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| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet YGV627.PDF ] | |
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