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PDF YMF721 Data sheet ( Hoja de datos )
| Número de pieza | YMF721 | |
| Descripción | FM + Wavetable Synthesizer LSI | |
| Fabricantes | LSI Computer Systems | |
| Logotipo |  |
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YMF721
OPL4-ML2
FM + Wavetable Synthesizer LSI
OVERVIEW
YMF721 (OPL4-ML2) is a high quality and low cost Wavetable synthesizer LSI. YMF721 (OPL4-ML2)
integrates an OPL3 (FM synthesizer), General MIDI processor and 1 Mbyte Wavetable sample ROM into one
chip, and complies with General MIDI (GM) system level 1. Thus, it is best suited to multimedia applications,
sound cards, MIDI synthesis modules and other sound applications.
Since this LSI outputs stereophonic 16 bit digital signal (fs = 44.1 kHz), it can be connected directly with
YMF701B, 711 or 715 (OPL3-SA, SA2 or SA3) or with YAC516(DAC16-L).
Operating voltage, 3.3 V, allows this LSI to be controlled with notebook personal computers.
Power management functions (power down and suspend/resume functions) of OPL4-ML2 contribute to low
power consumption of personal computers into which this product is built-in.
FEATURES
• The Wavetable synthesizer of this LSI is able to generate up to 24 types of sounds simultaneously.
• Has an interface that makes this LSI compatible with MPU-401 UART mode.
• Has an OPL3 (FM synthesizer) for AdLib/Sound Blaster applications.
• Has a 1 Mbyte built-in Wavetable sample ROM.
• Complies with GM system Level 1. (Thus, it is compatible with DOS applications that support MPU-401.)
• MIDI signal can be transmitted either through serial input or parallel input.
• FM synthesizer and Wavetable synthesizer of this LSI can generate their sound at the same time.
• FM synthesizer is register-compatible with OPL3.
• All registers are readable.
• Power management functions included power down and suspend/resume can be supported.
• Frequency of master clock signal is 33.8688 MHz.
• Pin compatible with YMF704C-S (100 pin SQPF)
• Voltage of power supply can be 5.0 V or 3.3 V.
• Silicone gate CMOS process
• 100-pin SQFP (YMF721-S).
GENERAL MIDI logo is a trademark of Association of Musical Electronics Industry (AMEI), and
indicates GM system level 1 Compliant.
YAMAHA CORPORATION
YMF721 CJuATlyAL1O0G, 1997
CATALOG No.:LSI-4MF721A20
Jury 10, 1997
1 page  
YMF721
BLOCK DIAGRAM
ADB[7-0]
A[2-0]
/MPUCS,/OPLCS
/IOW,/IOR
RST
/RESETSEL
FSP
RXD
XI
XO
ISA BUS
Interface
Decode
Logic
Timing
Generator
UART
Register
Control
(MPU/Command
/Control)
Synthesizer
Interface
(arbitration etc.)
TEST
Logic
Micro Processor
MIDI Interpreter
Command Interpreter
SRAM
32kbit
ROM
256kbit
Wave ROM
1M byte
Wavetable
Synthesizer
OPL3
FM Synthesizer
DO3
DO1
DO2
DO0
/PDOUT
CLKO
BCO
LRO
WCO
- 5 - July 10, 1997
5 Page 
YMF721
4. MIDI Interface
MIDI serial data can be inputted from RXD pin. It is necessary to input MIDI data complied with MIDI
1.0 detailed specification to RXD pin.
The serial data is the rate of 31.25kbit/sec (+/-1%) and the unit of 10 bits. The first bit is a start bit, the
next 8 bits are data (LSB to MSB), and the 10th bit is a stop bit.
5. Power management functions
YMF721 (OPL4-ML2) has two types of power management functions as follows.
(1) Global power down mode
(2) Suspend/Resume mode
5-1. Global power down mode
Generation of clock signal is disabled (stopped). Total power consumption of YMF721 (OPL4-ML2) is
approximately 20uA (typ.). Writing "FDh" into command register or receiving System Exclusive MIDI
Message makes in this mode. YMF721 (OPL4-ML2) outputs "L" from /PDOUT pin in this mode,
which can be used as power down control signal for peripheral equipment. Set KON bit (FM
synthesizer register) to "0" for all channels before going into this mode. Check that play back of MIDI
data is stopped.
/RESETSEL pin has a built-in pull up resistor. When this pin is at "L" in this mode, the power
consumption is higher by approximately 30uA than the one when this pin is open or at "H".
5-1-1. ISA BUS Connect System
When "FDh" has been written into command register, the internal processor goes into the global power
down mode after performing the following internal processes.
1) Disabling synthesizer's internal clock
2) Setting GBUSY bit of status register to "0".
YMF721 (OPL4-ML2) requires over 30 msec to complete the above processes before going into the
power down mode.
Since generation of the clock has been disabled, recovery from the power down mode can not be made
by using command. Thus, it is necessary to use PDY and PDX bits of control register for the recovery.
To resume normal operation through the recovery sequence, waiting time of 50 to 100 msec is required
before the oscillation of crystal stabilizes when internal oscillation is used, or 3 msec or more before
the recovery of clock generated in the synthesizer.
For the details of power down command, refer to 6-3. After the power down command, FDh, has been
written, do not write any command before sending a recovery command to the control register to return
to the normal mode.
- 11 -
July 10, 1997
11 Page | ||
| Páginas | Total 41 Páginas | |
| PDF Descargar | [ Datasheet YMF721.PDF ] | |
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