PDF ZL30409 Data sheet ( Hoja de datos )

Número de pieza	ZL30409
Descripción	T1/E1 System Synchronizer with Stratum 3 Holdover
Fabricantes	Zarlink Semiconductor Inc
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Features • Supports Telcordia GR-1244-CORE Stratum 4 timing for DS1 interfaces • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interfaces • Selectable 19.44 MHz, 2.048MHz, 1.544MHz or 8kHz input reference signals • Provides C1.5, C2, C4, C6, C8, C16, and C19 (STS-3/OC3 clock divided by 8) output clock signals • Provides 5 styles of 8 KHz framing pulses • Holdover frequency accuracy of 0.05 PPM • Holdover indication • Attenuates wander from 1.9Hz • Fast lock mode • Provides Time Interval Error (TIE) correction • Accepts reference inputs from two independent sources • JTAG Boundary Scan ZL30409 T1/E1 System Synchronizer with Stratum 3 Holdover Data Sheet November 2003 Ordering Information ZL30409/DDA 48 pin SSOP ZL30409/DDB 48 pin SSOP (Tape and Reel) -40°C to +85°C Applications • Synchronization and timing control for multitrunk T1,E1 and STS-3/OC3 systems • ST-BUS clock and frame pulse sources Description The ZL30409 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The ZL30409 generates ST-BUS clock and framing signals that are phase locked to either a 19.44 MHz, 2.048MHz, 1.544MHz, or 8kHz input reference. TCK TDI TMS TRST TDO PRI SEC RSEL OSCi OSCo TCLR LOCK Master Clock IEEE 1149.1a Reference Select MUX TIE Corrector Circuit Selected Reference Virtual Reference Reference Select TIE Corrector Enable State Select DPLL State Select Input Impairment Monitor Control State Machine Feedback VDD GND Output Interface Circuit Frequency Select MUX C19o C1.5o C2o C4o C6o C8o C16o F0o F8o F16o RSP TSP MS1 MS2 RST HOLDOVER PCCi FLOCK FS1 FS2 Figure 1 - Functional Block Diagram Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912, France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved. 1 page ZL30409 Data Sheet Pin Description (continued) Pin # 45 46 47 48 Name Description TDI TRST TCK TMS Test Serial Data In (Input). JTAG serial test instructions and data are shifted in on this pin. This pin is internally pulled up to VDD. Test Reset (Input). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. If not used, this pin should be held low. Test Clock (Input): Provides the clock to the JTAG test logic. This pin is internally pulled up to VDD. Test Mode Select (Input). JTAG signal that controls the state transitions of the TAP controller. This pin is internally pulled up to VDD. Functional Description The ZL30409 is a System Synchronizer, providing timing (clock) and synchronization (frame) signals to interface circuits for T1 and E1 Primary Rate Digital Transmission links. Figure 1 is a functional block diagram which is described in the following sections. Reference Select MUX Circuit The ZL30409 accepts two simultaneous reference input signals and operates on their falling edges. Either the primary reference (PRI) signal or the secondary reference (SEC) signal can be selected as input to the TIE Corrector Circuit. The selection is based on the Control, Mode and Reference Selection of the device. See Table 1 and Table 4. Frequency Select MUX Circuit The ZL30409 operates with one of four possible input reference frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz). The frequency select inputs (FS1 and FS2) determine which of the four frequencies may be used at the reference inputs (PRI and SEC). Both inputs must have the same frequency applied to them. A reset (RST) must be performed after every frequency select input change. See Table 1. FS2 FS1 Input Frequency 00 19.44MHz 01 8kHz 10 1.544MHz 11 2.048MHz Table 1 - Input Frequency Selection Time Interval Error (TIE) Corrector Circuit The TIE corrector circuit, when enabled, prevents a step change in phase on the input reference signals (PRI or SEC) from causing a step change in phase at the input of the DPLL block of Figure 1. During reference input rearrangement, such as during a switch from the primary reference (PRI) to the secondary reference (SEC), a step change in phase on the input signals will occur. A phase step at the input of the DPLL would lead to unacceptable phase changes in the output signal. 5 Zarlink Semiconductor Inc. 5 Page ZL30409 Data Sheet ZL30409 Measures of Performance The following are some synchronizer performance indicators and their corresponding definitions. Intrinsic Jitter Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output. It is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter may also be measured when the device is in a non-synchronizing mode, such as free running or holdover, by measuring the output jitter of the device. Intrinsic jitter is usually measured with various bandlimiting filters depending on the applicable standards. In the ZL30409, the intrinsic Jitter is limited to less than 0.02UI on the 2.048MHz and 1.544MHz clocks. Jitter Tolerance Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied jitter magnitude and jitter frequency depends on the applicable standards. Jitter Transfer Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. The ZL30409 jitter transfer is determined by the Loop Filter corner frequency (1.9Hz). The ZL30409 has twelve outputs with three possible input frequencies (except for 19.44MHz, which is internally divided to 8KHz) for a total of 36 possible jitter transfer functions. Since all outputs are derived from the same signal, the jitter transfer values for the four cases, 8kHz to 8kHz, 1.544MHz to 1.544MHz and 2.048MHz to 2.048MHz can be applied to all outputs. It should be noted that 1UI at 1.544MHz is 644ns, which is not equal to 1UI at 2.048MHz, which is 488ns. Consequently, a transfer value using different input and output frequencies must be calculated in common units (e.g., seconds) as shown in the following example. What is the T1 and E1 output jitter when the T1 input jitter is 20UI (T1 UI Units) and the T1 to T1 jitter attenuation is 18dB?   –-2---A0--  OutputT1 = InputT1×10   –--2--1-0--8- OutputT1 = 20×10 = 2.5UI(T1) OutputE1 = Out putT1 × (---1---U-----I--T----1----) (1UIE1) OutputE1 = OutputT1 × ((---64---48---48---nn----ss--))-= 3.3UI(T1) Using the above method, the jitter attenuation can be calculated for all combinations of inputs and outputs based on the three jitter transfer functions provided. Note that the resulting jitter transfer functions for all combinations of inputs (8kHz, 1.544MHz, 2.048MHz and 19.44MHz) and outputs (8kHz, 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz, 19.44MHz) for a given input signal (jitter frequency and jitter amplitude) are the same. 11 Zarlink Semiconductor Inc. 11 Page

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